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我在ubuntu上装了vcs_vC-2009.06,但运行时候出错,没有波形文件也没有任何.v中应打印出来的信息~
运行过程中,产生的提示信息如下:
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Command: vcs -f ./../scr/asynFIFO.f +notimingcheck +nospecify +v2k -debug_all -l \
./../logs/compile.log -Mdir=./DATA -P /home/microe/data/program/eda_linux/debussy/debussy-52v15-basic/share/PLI/vcs/LINUX/debussy.tab \
/home/microe/data/program/eda_linux/debussy/debussy-52v15-basic/share/PLI/vcs/LINUX/pli.a \
-ucli -l ./../logs/asynFIFO.vcs.log
Chronologic VCS (TM)
Version C-2009.06 -- Sat Jan 30 13:25:55 2010
Copyright (c) 1991-2008 by Synopsys Inc.
ALL RIGHTS RESERVED
This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.
Warning-[ILLGO] Invalid option used
Invalid option '-2001' must be ignored.
Please check vcs -help for supported options.
Parsing design file '/home/microe/data/digital/asynFIFO/src/asynFIFO.v'
Parsing design file '/home/microe/data/digital/asynFIFO/src/asynFIFO_ctrl.v'
Parsing design file '/home/microe/data/digital/asynFIFO/src/asynFIFO_tbw.v'
Parsing design file '/home/microe/data/digital/asynFIFO/src/bcd2gray.v'
Parsing design file '/home/microe/data/digital/asynFIFO/src/dpram.v'
Parsing design file '/home/microe/data/digital/asynFIFO/src/gray2bcd.v'
Top Level Modules:
asynFIFO_tbw
No TimeScale specified
Starting vcs inline pass...
1 module and 0 UDP read.
recompiling module asynFIFO_tbw because:
This module or some inlined child module(s) has/have been modified.
make[1]: Entering directory `/home/microe/data/digital/asynFIFO/sim/DATA'
gcc -pipe -O -I/home/microe/data/program/eda_linux/synopsys/vcs/vcs_vC-2009.06_common/vcs/include \
-c -o rmapats.o rmapats.c
if [ -x /home/microe/data/digital/asynFIFO/sim/simv ]; then chmod -x /home/microe/data/digital/asynFIFO/sim/simv; \
fi
g++ -o /home/microe/data/digital/asynFIFO/sim/simv 5NrI_d.o 5NrIB_d.o 95pg_1_d.o \
rmapats_mop.o rmapats.o SIM_l.o /home/microe/data/program/eda_linux/synopsys/vcs/vcs_vC-2009.06_common/vcs/linux/lib/libvirsim.a \
/home/microe/data/program/eda_linux/synopsys/vcs/vcs_vC-2009.06_common/vcs/linux/lib/librterrorinf.so \
/home/microe/data/program/eda_linux/synopsys/vcs/vcs_vC-2009.06_common/vcs/linux/lib/libsnpsmalloc.so \
/home/microe/data/program/eda_linux/debussy/debussy-52v15-basic/share/PLI/vcs/LINUX/pli.a \
/home/microe/data/program/eda_linux/synopsys/vcs/vcs_vC-2009.06_common/vcs/linux/lib/libvcsnew.so \
/home/microe/data/program/eda_linux/synopsys/vcs/vcs_vC-2009.06_common/vcs/linux/lib/vcs_save_restore_new.o \
/home/microe/data/program/eda_linux/synopsys/vcs/vcs_vC-2009.06_common/vcs/linux/lib/ctype-stubs_32.a \
-ldl -lm -lm -lc -lpthread -ldl
/home/microe/data/digital/asynFIFO/sim/simv up to date
make[1]: Leaving directory `/home/microe/data/digital/asynFIFO/sim/DATA'
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最佳答案
查看完整内容
+v2k应该是-2001的原因,但是你不用管,因为已经被ignore了,相当于没有加-2001这个option,而且你一个AsyncFIFO不会用generic这种语法吧(他没报错就表示编译成功了)。
然后你执行./simv来运行编译好的文件,有错误吗?我没看到你的log文件,你试着在testbench里打印一行话如“hello” 试试,如果能正常打印出来,但是没波图,说明你debussy的接口有问题。
最后,希望你发现问题后能逐步排除,最后确定产生问题的原因,再解决 ...
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