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本文以加法为例:
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adder.c
---------------------------------------------------
void adder(int a, int b, int *sum)
{
*sum = a + b;
}
---------------------------------------------------
HLS工具(AutoPilot)综合之后的结果:
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adder.v
---------------------------------------------------
`timescale 1 ns / 1 ps
module adder (
a,
b,
sum
);
input [31:0] a;
input [31:0] b;
output [31:0] sum;
assign sum = (b + a);
endmodule //adder
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adder.vhd
---------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.AESL_components.all;
entity adder is
port (
a : IN STD_LOGIC_VECTOR (31 downto 0);
b : IN STD_LOGIC_VECTOR (31 downto 0);
sum : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of adder is
begin
sum <= esl_add(b, a);
end behav;
---------------------------------------------------
备注:加减乘除、位运算、逻辑运算等等基本的C/C++运算都可以很方便的用AutoPilot综合成对应的RTL代码(verilog/vhdl)
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