Aldec Riviera-PRO 2009.02

godsnake · 发表于 2010-1-20 13:54:37

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Riviera-PRO 2009.10 Download Configurations Brochure (.pdf)

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Large FPGA and ASIC VerificationRiviera-PRO is a multi-platform, high-performance, mixed-language RTLand gate-level simulator for ASIC and FPGA designs. Riviera-PROincludes advanced debugging tools and support of advanced verificationwith SystemC and SystemVerilog, Assertions Based Verification (ABV),Transaction Level Modeling (TLM) and VHDL/Verilog Design Rule Checking.Riviera-PRO works in command line mode and in GUI with easy switchingbetween the two.

Top Features

Common-Kernel VHDL, Verilog®, SystemVerilog, SystemC/C/C++/TLM 2.0, EDIF Simulator
32 and 64 bit simulation
SystemVerilog, PSL and OVA Assertions and Functional Coverage
Code Coverage: Statement, Expression, Condition, Branch, Toggle & Path
Unified HDL/SystemC code level debugging
Accelerated Waveform Viewer
VHDL and Verilog Code Checking (Lint)
Fast, kernel-level co simulation with MATLAB®
Script compatible with other HDL simulators
Linux and Windows® 7/Vista/XP/2003 32/64 bit support