没有看到笑脸 ,可见有错误的,报告里面有这下面两个错误
Error:
Different numbers of ports (see below).
Power net missing in layout. Ground net missing in layout.
我在版图里面画了四个pin,分别为vdd gnd 还有输入输出 A ,OUT
端口都是对着的怎么会出现不同的ports,还有power 和Ground是怎么回事?
用candence提取的网表为:
************************************************************************
* auCdl Netlist:
*
* Library Name:
test
* Top Cell Name: inv
* View Name:
schematic
* Netlisted on:
Dec 28 01:17:53 2009
************************************************************************
######C A L I B R E S Y S T E M
###### L V SR E P O R T
######
##################################################
REPORT FILE NAME:inv.lvs.report
LAYOUT NAME:inv.sp ('inv')
SOURCE NAME:netlist ('inv')
RULE FILE:/home/eda/_chrt035rf.sg.lvs.cal_
RULE FILE TITLE:
Mentor Calibre LVS Runset for Chartered 0.35um Analog/RF Single Gate (3.3V) Process
CREATION TIME:Mon Dec 28 01:54:26 2009
CURRENT DIRECTORY:/home/eda
USER NAME:eda
CALIBRE VERSION:v2006.1_25.26
Thu Apr
6 13:20:44 PDT 2006
OVERALL COMPARISON RESULTS
##########################
# #####NOT COMPARED
## #############################
Error:
Different numbers of ports.
Error:
Power or ground net missing.
**************************************************************************************************************CELLSUMMARY
**************************************************************************************************************
Result Layout Source
NOT COMPARED inv inv
**************************************************************************************************************
CELL COMPARISON RESULTS ( TOP LEVEL )
######################### ###
##NOT COMPARED
## ###########################
Error:
Different numbers of ports (see below).
Error:
Power net missing in layout. Ground net missing in layout.
LAYOUT CELL NAME:inv
SOURCE CELL NAME:inv
-------------------------------------------------------------------------------------------------------------
INITIAL NUMBERS OF OBJECTS
--------------------------
NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------
Layout Source Component Type
Ports: 0 4
Nets: 4 4
Instances:1 0 MN (4 pins)
1 0 MP (4 pins)
0 1 INV (2 pins): output input
Total Inst: 2 1
* = Number of objects in layout different from number in source.
*************************************************************************************************************
SUMMARY
**************************************************************************************************************
Total CPU Time:
0 sec
Total Elapsed Time:
1 sec