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发表于 2009-12-21 12:26:21
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Evolution of the mobile communication standards and proliferation of hand-
held devices mandate stringent Analog-to-Digital Converter (ADC) speci¯cations.
Among various ADCs, a ¢§ ADC is best known as a power-e±cient ADC when
more than 12b is required. However, a conventional discrete-time (DT) ¢§ Modu-
lator (¢§M) is inadequate for low-power wideband applications due to the opamp
settling requirement. Alternatively, a continuous-time (CT) ¢§M can be used
to decrease power consumption but has its own disadvantages such as clock jitter
sensitivity, RC time constant variation, and excess loop delay.
The wideband modulators are often implemented as single-loop high-order
modulators in a deep submicron process. The high-order modulator typically has a
quantizer overloading problem as the input signal approaches to a full-scale range.
A pole-optimization method can be used to extend the linear input range but it
inevitably decreases signal to quantization noise ratio. This causes power penalty
since it limits the maximum input power available. |
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