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用verilog编写的时序电路编译通过了，但是就是没有波形，所以想请教大虾我的问题出在那里？时序电路主要是想通过计数的方法来得到想要的波形，代码如下：
`timescale 1ns / 1ps
module control_panel_write_sram(clk40,rst,FLAGB,
clk_irst,clk_shr,clk_intg,clk_shs,clk_sti,clk_clk);
input clk40; //输入时钟40M
input rst;
input FLAGB;
output clk_irst;
output clk_shr;
output clk_intg;
output clk_shs;
output clk_sti;
output clk_clk;
reg flagb;
reg clk20;
reg clk_irst;
reg clk_shr;
reg clk_intg;
reg clk_shs;
reg clk_sti;
reg clk_clk;
reg clk_clk_en;
reg AFE_CS;
reg AFE_NS;
reg [11:0] count_clk_AFE;
reg [2:0] count_clk_sti;
reg [9:0] count_600;
reg [8:0] count_clk_clk;
reg [9:0] count_clk_down;
reg [2:0] count_clk_shr;
reg [2:0] count_clk_intg;
reg [9:0] count_clk_tft;
reg [6:0] count_clk_shs1;
reg [2:0] count_clk_shs2;
reg [2:0] count_clk_shs3;
parameter AFE_IDLE = 12'b000000000001;
parameter AFE_SET = 12'b000000000010;
parameter STI_DOWN = 12'b000000000100;
parameter IRST_DOWN_CLK_UP = 12'b000000001000;
parameter CLK_33_EN = 12'b000000010000;
parameter SHR_UP = 12'b000000100000;
parameter INTG_DOWN = 12'b000001000000;
parameter INTG_UP = 12'b000010000000;
parameter SHS_DOWN = 12'b000100000000;
parameter SHS_UP = 12'b001000000000;
parameter ONE_PULSE_END = 12'b010000000000;
parameter AFE_HALL = 12'b100000000000;
always @ (posedge clk40 or negedge rst)
begin
if(!rst)
flagb<=0;
else
flagb<=FLAGB;
end
////////////////////////////////////////////clk20 pulse
always@ (posedge clk40 or negedge rst )
begin
if(!rst)
clk20<=0;
else if(flagb==1)
begin
clk20<=~clk20;
end
end
//////////////////////////////////EOC count when 600 then stop read
always@ (posedge clk_clk or negedge rst )
begin
if(!rst)
count_600<=0;
else if(flagb==1)
begin
count_600<=count_600+1;
end
end
////////////////////////////////////////////AFE STATE MACHINE
always @(posedge clk20 or negedge rst)
begin
if(~rst)
AFE_CS<=AFE_IDLE;
else
AFE_CS<=AFE_NS;
end
always @(AFE_CS or flagb or count_clk_sti or count_clk_clk or count_clk_down or count_clk_shr or count_clk_intg or count_clk_tft or count_clk_shs1 or count_clk_shs2 or count_clk_shs3 )
begin
case(AFE_CS)
AFE_IDLE:
begin
if(flagb==1)
AFE_NS=AFE_SET;
else
AFE_NS=AFE_IDLE;
end
AFE_SET:
begin
if(count_clk_sti==3'b100) // 4)
AFE_NS=STI_DOWN;
else
AFE_NS=AFE_SET;
end
STI_DOWN:
begin
AFE_NS=IRST_DOWN_CLK_UP;
end
IRST_DOWN_CLK_UP:
begin
if(count_clk_clk==9'b101001001) //329)
AFE_NS=CLK_33_EN;
else
AFE_NS=IRST_DOWN_CLK_UP;
end
CLK_33_EN:
begin
if(count_clk_down== 10'b1000001011) //523)
AFE_NS=SHR_UP;
else
AFE_NS=CLK_33_EN;
end
SHR_UP:
begin
if(count_clk_shr== 3'b100) //4)
AFE_NS=INTG_DOWN;
else
AFE_NS=SHR_UP;
end
INTG_DOWN:
begin
if(count_clk_intg==3'b100) //4)
AFE_NS=INTG_UP;
else
AFE_NS=INTG_DOWN;
end
INTG_UP:
begin
if(count_clk_tft==10'b1111110001) //1009)
AFE_NS=SHS_DOWN;
else
AFE_NS=INTG_UP;
end
SHS_DOWN:
begin
if(count_clk_shs1==7'b1101101) //109)
AFE_NS=SHS_UP;
else
AFE_NS=SHS_DOWN;
end
SHS_UP:
begin
if(count_clk_shs2== 3'b100) //4)
AFE_NS=ONE_PULSE_END;
else
AFE_NS=SHS_UP;
end
ONE_PULSE_END:
begin
if(count_600<599)
begin
if(count_clk_shs3==4 && flagb==1)
AFE_NS=AFE_SET;
else
AFE_NS=ONE_PULSE_END;
end
else
AFE_NS=AFE_HALL;
end
AFE_HALL:
AFE_NS=AFE_HALL;
default:
AFE_NS=AFE_IDLE;
endcase
end
//**************state machine output***********************
always @(posedge clk20 or negedge rst)
begin
if(~rst)
begin
clk_irst<=0;
clk_shr<=0;
clk_intg<=0;
clk_shs<=0;
clk_sti<=0;
clk_clk<=0;
clk_clk_en<=0;
count_clk_AFE<=12'b0;
count_clk_sti<=3'b0;
count_clk_clk<=9'b0;
count_clk_down<=10'b0;
count_clk_shr<=3'b0;
count_clk_intg<=3'b0;
count_clk_tft<=10'b0;
count_clk_shs1<=10'b0;
count_clk_shs2<=3'b0;
count_clk_shs3<=3'b0;
end
else
begin
case(AFE_NS)
AFE_IDLE:
begin
clk_irst<=0;
clk_shr<=0;
clk_intg<=0;
clk_shs<=0;
clk_sti<=0;
clk_clk<=0;
clk_clk_en<=0;
count_clk_AFE<=12'b0;
count_clk_sti<=3'b0;
count_clk_clk<=9'b0;
count_clk_down<=10'b0;
count_clk_shr<=3'b0;
count_clk_intg<=3'b0;
count_clk_tft<=10'b0;
count_clk_shs1<=10'b0;
count_clk_shs2<=3'b0;
count_clk_shs3<=3'b0;
end
AFE_SET:
begin
clk_irst<=1;
clk_sti<=1;
count_clk_sti=count_clk_sti+1;
end
STI_DOWN:
begin
clk_sti<=0;
end
IRST_DOWN_CLK_UP:
begin
clk_irst<=0;
clk_clk_en<=1;
count_clk_clk=count_clk_clk+1;
end
CLK_33_EN:
begin
clk_clk_en<=0;
count_clk_down=count_clk_down+1;
end
SHR_UP:
begin
clk_shr<=1;
count_clk_shr=count_clk_shr+1;
end
INTG_DOWN:
begin
clk_shr<=0;
count_clk_intg=count_clk_intg+1;
end
INTG_UP:
begin
clk_intg<=1;
count_clk_tft=count_clk_tft+1;
end
SHS_DOWN:
begin
clk_intg<=0;
count_clk_shs1=count_clk_shs1+1;
end
SHS_UP:
begin
clk_shs<=1;
count_clk_shs2=count_clk_shs2+1;
end
ONE_PULSE_END:
begin
clk_shs<=0;
count_clk_shs3=count_clk_shs3+1;
end
AFE_HALL:
begin
clk_irst<=0;
clk_shr<=0;
clk_intg<=0;
clk_shs<=0;
clk_sti<=0;
clk_clk<=0;
clk_clk_en<=0;
count_clk_AFE<=12'b0;
count_clk_sti<=3'b0;
count_clk_clk<=9'b0;
count_clk_down<=10'b0;
count_clk_shr<=3'b0;
count_clk_intg<=3'b0;
count_clk_tft<=10'b0;
count_clk_shs1<=10'b0;
count_clk_shs2<=3'b0;
count_clk_shs3<=3'b0;
end
default:
begin
clk_irst<=0;
clk_shr<=0;
clk_intg<=0;
clk_shs<=0;
clk_sti<=0;
clk_clk<=0;
clk_clk_en<=0;
count_clk_AFE<=12'b0;
count_clk_sti<=3'b0;
count_clk_clk<=9'b0;
count_clk_down<=10'b0;
count_clk_shr<=3'b0;
count_clk_intg<=3'b0;
count_clk_tft<=10'b0;
count_clk_shs1<=10'b0;
count_clk_shs2<=3'b0;
count_clk_shs3<=3'b0;
end
endcase
end
end
endmodule
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发表于 2009-12-15 11:13:01
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