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Abstract
THE IMPORTANCE OF CMOS TECHNOLOGY is increasing in RF design applications
owing to the promise of integrating electronic systems on a single silicon
chip. While complete broad band characterization and accurate modeling of the MOSFET
noise are critical requirements for circuit designs, the noise behavior and physics in short
channel MOSFETs is not well understood. This dissertation explores the physical origin
and contributing mechanisms of noise in MOSFETs, as well as a design methodology to
minimize the impact of noise on fully integrated LNAs.
Investigating the physical noise sources in the MOSFET imposes significant computational
requirements, due to the multi-dimensional nature of the device. In addition, higher
order transport models need to be considered due to aggressive channel-length scaling.
This dissertation presents a quasi two-dimensional noise simulation technique which provides
an accurate and fast solution for MOSFET noise analysis by combining a 1-D active
transmission line model with rigorous 2-D device simulation.
The physical origin of the excess noise in short channel MOSFETs has been identified.
Source-side contributions dominate drain current noise; non-local transport behavior
causes higher local ac resistance near the source junction and in turn generates extra noise
contributions which are amplified by the channel transconductance. This phenomenon is
directly reflected in excess values and a strong gate length dependence of γ and δ in scaled
submicron MOSFETs. Higher order transport models are essential to capture this effect in
noise simulation.
Contrary to the common assumption that drain current exhibits only 1/f and white
channel thermal noise contributions, this study demonstrates that the substrate generates
thermal fluctuations that produce additive channel noise, amplified by the substrate transconductance.
This component produces another plateau and frequency dependence in the noise
spectrum of the drain current. Moreover, the effect tends to exaggerate the drain noise factor
at low frequencies.
The high frequency noise modeling for MOSFET devices generally requires at least
three parameters. This study demonstrates that while other two-parameter approaches, such
as developed by Pospieszalski and those used in BSIM4 model, lead to errors, the results
do not cause noticeable discrepancies for most practical circuit topologies. The modeling
approach used in BSIM4 has been independently validated and is shown to be sufficient in
capturing the physical origin of the excess noise.
Explicit guidelines for LNA design have been presented based directly on measured
noise parameters and two-port noise theory; the approach requires neither sophisticated
noise modeling nor circuit simulation. An 800MHz LNA test chip has been designed based
on the proposed methodology. With 3.75mA of bias current, the LNA achieves about 0.9dB
of noise figure, which adds just 0.3dB to the NFmin of the intrinsic MOSFET device. It is
competitive with that of GaAs and bipolar LNAs and also quite close to the values predicted
using the analysis presented in this work. |
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发表于 2006-8-9 09:16:14
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