PFD型PLL设计遇到的问题

小小xxl

只有两频率相等时才锁定，但是频率不等时能给出误差电压，所以我觉得只要voc能调节过去锁相环能最终锁上
rguc 发表于 2009-11-22 17:12

                               
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恩，就是啊。我也觉得是这样子的！呵呵，哪就先这样认为算了！哈哈

mmic1978

best book has good option on this

leeeweimin

http://www.google.com.hk/search?sourceid=chrome&ie=UTF-8&q=PFD+PLL+theoryPhase Frequency Detectors (PFD)
The phase detector generates the error signal required in the feedback loop of the synthesizer. The majority of PLL ASICs use a circuit called a Phase Frequency Detector (PFD) similar to the one shown in Figure 6. Compared with mixers or XOR gates, which can only resolve phase differences in the +/- p range, the PFD can resolve phase differences in the +/- 2p range or more (typically “frequency difference” is used to describe a phase difference of more than 2p, hence the term “phase frequency detector.” This circuit shortens transient switching times and performs the function in a simple and elegant digital circuit.

                               
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The PFD compares the reference signal Fr with that of the divided down VCO signal (Fvco/N) and activates the charge pumps based on the difference in phase between these two signals. The operational characteristics of the phase detector circuitry can be broken down into three modes: frequency detect, phase detect, and phase locked mode. When the phase difference is greater than ±2p, the device is considered to be in frequency detect mode. In frequency detect mode the output of the charge pump will be a constant current (sink or source, depending on which signal is higher in frequency.)
The loop filter integrates this current and the result is a continuously  hanging control voltage applied to the VCO. The PFD will continue to operate in this mode until the phase error between the two input signals drops below 2p.

leeeweimin

http://www.google.com.hk/search?sourceid=chrome&ie=UTF-8&q=PFD+PLL+theoryPhase Frequency Detectors (PFD)
The phase detector generates the error signal required in the feedback loop of the synthesizer. The majority of PLL ASICs use a circuit called a Phase Frequency Detector (PFD) similar to the one shown in Figure 6. Compared with mixers or XOR gates, which can only resolve phase differences in the +/- p range, the PFD can resolve phase differences in the +/- 2p range or more (typically “frequency difference” is used to describe a phase difference of more than 2p, hence the term “phase frequency detector.” This circuit shortens transient switching times and performs the function in a simple and elegant digital circuit.

                               
登录/注册后可看大图

The PFD compares the reference signal Fr with that of the divided down VCO signal (Fvco/N) and activates the charge pumps based on the difference in phase between these two signals. The operational characteristics of the phase detector circuitry can be broken down into three modes: frequency detect, phase detect, and phase locked mode. When the phase difference is greater than ±2p, the device is considered to be in frequency detect mode. In frequency detect mode the output of the charge pump will be a constant current (sink or source, depending on which signal is higher in frequency.)
The loop filter integrates this current and the result is a continuously  hanging control voltage applied to the VCO. The PFD will continue to operate in this mode until the phase error between the two input signals drops below 2p.

lynn_net

不错！

zjt289198457

我想请问一个问题，对于环路滤波器的带宽有没有参考的确认方法或者公式来计算一个带宽值！

lovlybigbear

看看吧