Nanometer MOS Current-Mode Logic

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Power-Aware Design Techniques for Nanometer MOS Current-Mode Logic Gates a Design Framework

Authors: Massimo Alioto & Gaetano Palumbo

IEEE CIRCUITS AND SYSTEMS MAGAZINE 2006 IEEE FOURTH QUARTER 2006

Abstract
In the recent years, MOS Current-Mode Logic (MCML) circuits have been gaining a remarkable interest in several VLSI applications, ranging from high-accuracy mixed-signal circuits to high-speed circuits for channel (de)multiplexing in optic fiber and Radio Frequency (RF) telecommunication systems. However, advantages over traditional CMOS logic are achieved at the cost of a static power consumption, which must be kept as low as possible. Accordingly, a conscious management of the powerdelay trade-off is essential in the design of such circuits. This paper presents several recent ideas on the design of digital MCML circuits organized in a comprehensive framework. The treatment reviews and extends previous results by incorporating Deep-Sub-Micron (DSM) effects from the beginning, with a strongly simplified analytical formulation to improve the understanding and the design. Interesting properties and design criteria are derived from simple analytical models. From these models, a deep insight into the design of MCML circuits is gained, which is essential for both the efficient design of MCML cells and the development of an automated design flow. Numerical examples are presented by considering a 90-nm CMOS process.

A1985

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jiansheng

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