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发表于 2006-10-30 13:28:59
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Cisco:
Hardware Engineers who participate in the design of complex, high performance and high integration ASICs used in Cisco storage/data center switch products. Implement Design for Test strategy into the ASICs and responsible for ASIC DFT sign off. Participate in driving new DFT methodology and solutions to improve quality of the ASIC, reliability and in system test and debug capability.
Daily responsibilities include:
¿ Implement basic DFT schemes in terms of BIST, scan, boundary scan on ASICs.
¿ Generate tests which achieve highest possible ASIC component test coverage with lowest overhead.
¿ Verify all DFT logics and test patterns with simulation and static timing analysis tool.
¿ Implement and verify advanced DFT logics like logic BIST, high speed interface test logic etc.
¿ Participate in new DFT methodology discussion and solution generation.
¿ Work with ASIC design team in ASIC bring up.
¿ Good knowledge in Design for Test in general. Understand the concepts of BIST, SCAN, Boundary Scan, ATPG.
¿ Experience in ASIC DFT design, Testability, and Reliability issues.
¿ Hands on familiarity with various ASIC DFT analysis, synthesis, and verification tools.
¿ Familiar with fault coverage and board/system testability analysis and enhancement technique, DFT economics analysis/justification technique.
¿ Hands on knowledge of simulation and verification debug tools.
¿ Good knowledge of test engineering in terms of ASIC test program generation, understanding of testers and associated hardware is a plus.
¿ Working knowledge using Verilog HDL languages and tools, scripting and programming languages (Perl, TCL, C and C++).
¿ Excellent written and verbal communications, team and people skills.
Typically requires MSEE/CS combined with 3-4 years experience, or BSEE/CS combined with 4-7+ yrs
[ 本帖最后由 jingli888ca 于 2006-10-30 13:38 编辑 ] |
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发表于 2006-10-19 22:31:40
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