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Job Responsibilities
Duties will include working within a Product Development Team to develop reusable block-level and ASIC testbenches using HVL. Develop new ASIC verification environments to support ASIC development. Maintain existing ASIC verification environments. Review RTL architectural and implementation specifications. Create stimulus drivers, monitors, dataflow models, and test plans to verify function and performance of advanced multiprotocol networking ASICs. Define and develop application tests required to verify ASICs meet functional and performance goals. Define and implement functional coverage plans. Define and implement code coverage plans. Develop testing and regression methodologies for new verification flow. Coordinate test plan implementation and regressions with remote team. Incorporate reusability into all aspects of the verification environment. Develop/maintain/enhance environment tools/scripts/makefiles.
Functional/Industry Knowledge
Required:
- Minimum of 4-6 years ASIC Verification experience in a product development environment
- Proven ASIC Design Verification skills
- Fluent in Verilog for design verification
- Experience with SpecMan
- Experience with one or more scripting languages: awk, Perl, python
- Experience with C/C++
- Superior debugging skills for large ASIC designs
- Knowledge of data and telecommunication networking(TDM/IP/ATM/Ethernet)
- Strong written and verbal communication skills in both Chineses and English
- Adaptable to evolving customer requirements
Desired:
- Past experience in a lead position giving guidance to other engineers
- Profound knoledge of DS3/E3
Education/Certifications
Required Degree: BS
Preferred Degree: MS
Preferred Major: Electrical Engineering or related discipline
MSN: shzhang2006@yahoo.com.cn
E-mail:shzhang2006@yahooo.com.cn |
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发表于 2006-7-19 11:41:33
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