This application note is written for logic designers who are new to HDL verification flows, and
who do not have extensive testbench-writing experience.[local]1[/local][local]1[/local]
Testbenches are the primary means of verifying HDL designs. This application note provides
guidelines for laying out and constructing efficient testbenches. It also provides an algorithm to
develop a self-checking testbench for any design.
/2 
eetop公众号
创芯大讲堂
创芯人才网
发表于 2009-10-21 08:30:43
