[转帖]EDA vendors reveal plans for SystemVerilog

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原文链接 ： http://www.eedesign.com/news/showArticle.jhtml?articleId=21402313
EDA vendors reveal plans for SystemVerilog
By Richard Goering
EE Times
m 08, 2004 (9:00 H EDT)   
   
SAN DIEGO, Calif. — 26 EDA vendors, along with silicon IP providers and training firms, revealed product plans for SystemVerilog support at an Accellera luncheon at the Design Automation Conference here Tuesday (June 8). Accellera also provided more justification for its controversial decision to donate SystemVerilog to a separate IEEE working group rather than the IEEE 1364 Verilog Standards Group.
The lunch event, entitled "Right Here! Right Now" featured "rapid fire" presentations from a number of vendor representatives, as well as a presentation from a user, Matt Maidment, senior CAD engineer at Intel Corp. It also included a review of technology enhancements in the latest SystemVerilog 3.1a release.
Dennis Brophy, Accellera chairman, said his organization decided to pursue standardization under the new IEEE Standards Association (IEEE-SA) because it offers a faster path to standardization. He said it offers improved efficiency, resulting in good "impedance matching" with Accellera. One difference from the IEEE 1364 group is the IEEE-SA's "one company, one vote" policy.
Brophy also said the IEEE-SA offers commercial backing in advance of a standard, and provides connections to international standards bodies. Still, critics fear that bypassing the IEEE 1364 group could result in two incompatible language standards.
Maidment said that SystemVerilog 3.1a offers three advantages over plain Verilog: better code, more reuse, and the chance for designers to capture more intent. Better code results from an ability to capture data relationships explicitly, and to use assertions to capture what shouldn't happen in the design, he said.
SystemVerilog enables reuse by allowing modular specifications, and by offering packages that facilitate type sharing, Maidment said. It lets designers express intent through new constructs and assertions, he said.
In addition to training and IP firms, SystemVerilog support announcements included the following. Cadence Design Systems, which has previously indicated its intent to support SystemVerilog, was notable by its absence.
@HDL — @Designer debugging tool, beta Q4 2004. @Verifier model checker, beta Q3 2004.
0-In — Archer-CDV verification tool, 3.1a support Q3 2004.
Aldec — Riviera simulator, synthesis constructs now, functional coverage by end of year.
Atrenta — PeriScope RTL analysis tool, 3.1a support March 2005.
Blue Pearl Software — upcoming functional/DFT closure tool, 3.1a Q4 2004. Upcoming timing constraint generator, 3.1a Q1 2005.
Bluespec — Bluespec Compiler and Simulator support most 3.1a design constructs today.
Denali — PureSpec verification IP and PureSuite compliance suite, 3.1a support Q4 2004.
EVE — ZeBu accelerator cosimulates 3.1a today through PLI, will cosimulate in Q1 2005 through transactors.
Fishtail — Focus timing constraint product, 3.1 assertion support already in place.
FTL Systems — Auriga design verification suite, 3.1a support Q4 2004.
Interra Systems — Cheetah-SV SystemVerilog front end, Beacon-SV SystemVerilog test suite, 3.1a support Q3 2004.
Jasper Design Automation — JasperGold formal verifier, SystemVerilog Q1 2005, assertions Q2 2005.
Lighthouse DA — inFact testbench synthesis, 3.1a support now.
Magma Design Automation — Blast Create synthesis, 3.1a Q3 2004.
Mentor Graphics — ModelSim simulator, full 3.1a beta support Q4 2004. FormalPro formal verifier, 3.1a support Q2 2005. Precision RTL synthesis, 3.1a support Q1 2005. HDL Designer, 3.1a support Q2 2005. Seamless HW/SW coverification, 3.1a beta Q4 2004. Advance mixed-signal simulation, 3.1a Q1 2005. VStation Pro emulator, 3.1a Q1 2005.
Novas Software — Verdi and Debussy debuggers, 3.1a assertions today, testbench by end of 2004.
Real Intent — Verix assertion-based verification, 3.1a assertions July 2004, full 3.1a Q4 2004.
Safelogic — Verifier property checker, 3.1a Q1 2005.
Summit Design — Visual Elite design and verification tool, 3.1 Q1 2005. HDL Score coverage tool, 3.1 Q2 2005.
Synapticad — TestBencher Pro, SystemVerilog support now.
Synopsys — VCS simulator, 3.1a complete Q4 2004. Design Compiler, 3.1a now. Magellan verification suite and Formality formal verifier, 3.1a in beta. Leda, 3.1a available now.
TransEDA — VN-Check rule checker, 3.1a Q3 2004. VN-Cover coverage tool, 3.1a end of 2004.
VeriEZ Solutions — EZTranslate Vera-to-SystemVerilog migration, Q4 2004.
Verific — parser, analyzer, elaborator for 3.0 and 3.1 assertions available now.
Verisity — SpeXsim testbench/simulation tool, SystemVerilog Q1 2005. SpecXtreme and Xtreme accelerators, Q2 2005.
Veritools — Undertow debugger, 3.1a September 2004.
Further SystemVerilog support information is available at Accellera's SystemVerilog web site. END

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