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请教版主及各位同行:
我在用vhdl语言编写一个曼切斯特收发器,其中编码部分间下面的程序:
本程序已通过仿真与综合,我想实现应该没有问题(以前做过类似的程序,且在电路板中工作很好),可是看过大公司用vhdl编写的不少代码,发现他们在进程中一般都用唯一的时钟信号作为边沿触发条件。对于器件外部及内部的信号,多半采用两个级连的FF来获得该信号的沿触发条件(同步化),结果增加了不少额外的寄存器资源,如果我能够保证时序正常的情况下,为什莫不直接利用该信号作为该进程的触发条件呢?以下程序都有哪些不规范呢???
希望各位大侠多多指点,让我从疑惑中解脱,不胜感激!!!!
--encode start
process(reset,EnEnd,EnEn)
begin
if reset = '1' or EnEnd = '1' then
EnTimeEn <= '0';
EnReset <= '1';
elsif EnEn'event and EnEn = '1' then
EnTimeEn <= '1';
EnReset <= '0';
end if;
end process;
--encode time divide
process (EnTimeEn, EnClk)
begin
if EnTimeEn = '0' then
EnCounts <= (others => '0');
esc <= '0';
elsif (EnClk'event and EnClk = '1' )then
if EnCounts = 2 then
EnCounts <= (others => '0');
esc <= not esc;
else
EnCounts <= EnCounts + 1;
end if;
end if;
end process;
--encode state machine
process(EnReset, esc)
variable EnBitNum : integer range 16 downto 0 ;
begin
if Enreset = '1' then
EnBitNum := 16;
EnEnd <= '0';
EnState <= EnSync1;
SendGate1 <= '0';
boo <= '1';
bzo <= '1';
elsif esc'event and esc ='1' then
case EnState is
when EnSync1 =>
SendGate1 <= '1';
if ss = '1' then
bzo <= '0';
boo <= '1';
else bzo <= '1';
boo <= '0';
end if;
EnState <= EnSync2;
when EnSync2 =>
EnState <= EnSync3;
when EnSync3 =>
EnState <= EnSync4;
when EnSync4 =>
if ss = '1' then
bzo <= '1';
boo <= '0';
else bzo <= '0';
boo <= '1';
end if;
EnState <= EnSync5;
when EnSync5 =>
EnState <= EnSync6;
when EnSync6 =>
EnState <= EnData0;
when EnData0 =>
if SendReg(EnBitNum) = '1' then
bzo <= '0';
boo <= '1';
else
bzo <= '1';
boo <= '0';
end if;
EnBitNum := EnBitNum - 1;
EnState <= EnData1;
when EnData1 =>
bzo <= not bzo;
boo <= not boo;
if EnBitNum = 0 then
EnState <= EnOk;
else
EnState <= EnData0;
end if;
when EnOk =>
bzo <= '1';
boo <= '1';
EnEnd <= '1';
when others => EnEnd <= '1';
end case;
end if;
end process; |
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