要设计一个13bit的DAC，有好多疑问，请大家指点迷津

shiyiru2007

本人没有做过DAC的设计，现在要做一个13bit的DAC，系统方案别人已经制定好，采用电流模式的R-2R结构，7+6分段：INL +-0.5LSB；DNL：+-1LSB：
我的疑问如下：
1 需要添加INL校正电路吗？需要的话在哪里能查找到校正电路的相关资料？
2应用只需要12bit，设计指标是12bit的话，样片是否很难达到12bit？
3 两个月完成线路设计是否可行？
4 采用电流模式的R-2R结构是否合适？sigma_delta是否更合适？

ulsi123

You need to tell us the DAC speed then I can give you some suggestions. I don't recommend you use R-2R structure for 12+ bit DAC as resistor matching could be a problem. For low speed and low power, sigma-delta wins. For high speed, go for current steering DAC.

[ 本帖最后由 ulsi123 于 2009-9-22 11:29 编辑 ]

shiyiru2007

原帖由 ulsi123 于 2009-9-22 10:39 发表

                               
登录/注册后可看大图

You need to tell us the DAC speed then I can give you some suggestions. I don't recommend you use R-2R structure for 12+ bit DAC as resistor matching could be a problem. For low speed and low power, s ...

3x very much！
input data rate最大是1.5KHz。 resistor matching 的问题能否用校正电路来解决？

ulsi123

Although resistor matching can be calibrated, I don't recommend you use such an architecture. The input data BW is only 1.5KHz, so you can easily use a sigma-delta modulator, maybe 2nd order is good enough to achieve 70dB SNR. The total power consumption should very low as well. There's a mistake in my previous posting, SAR is not for DAC, but for ADC, sorry.