LVS问题

yanzi123

CDL:
.subckt INV2V1 ZN A VV
*.NOPIN gnd vcc vcc vdd
*.PININFO ZN:O A:I VV:I
MP0 ZN A VV VV p w=2u l=0.8u
MN0 ZN A gnd gnd n w=1u l=0.8u
.ends INV2V1
模型为:

*********************************************************************
.LIB MOS
*==================================================
*===============<< 5VGS/5VDS NMOS >>===============
*==================================================
.subckt n d g s b l=20u w=20u dtemp=0 ad=0 as=0 pd=0 ps=0
mcore1 d g s b nch_core w='w' l='l' m=1
+ ad='(ad?ad1.3e-6*w))' pd='(pd?pd:2*(6.5e-7+w))' as='(as?as1.3e-6*w))' ps='(ps?ps:2*(6.5e-7+w))'         
.ends n
*==================================================
*===============<< 5VGS/5VDS Isolation NMOS >>=====
*==================================================
.subckt nchi d g s b iso l=20u w=20u dtemp=0 ad=0 as=0 pd=0 ps=0 area_bd=0 pj_bd=0 area_iso=0 pj_iso=0
mcore1 d g s b nch_core w='w' l='l' m=1 dtemp=dtemp
+ ad='(ad?ad1.3e-6*w))' pd='(pd?pd:2*(6.5e-7+w))' as='(as?as:(1.3e-6*w))' ps='(ps?ps:2*(6.5e-7+w))'  
dhpw_nbl b iso hpwdio_core  m=1 dtemp=dtemp
+ area='(area_bd?area_bd:((w+1.2e-5)*(l+1.75e-5)))'   pj='(pj_bd?pj_bd:(2*((w+1.2e-5)+(l+1.75e-5))))'
dnbl_sub psub iso nbldio_core m=1 dtemp=dtemp
+ area='(area_iso?area_iso:((w+3.2e-5)*(l+3.75e-5)))' pj='(pj_iso?pj_iso:(2*((w+3.2e-5)+(l+3.75e-5))))'
.ends nchi
*==================================================
*===============<< 5VGS/5VDS PMOS >>===============
*==================================================
.subckt p d g s b l=20u w=20u  dtemp=0 ad=0 as=0 pd=0 ps=0
mcore2 d g s b pch_core w='w' l='l' m=1 dtemp=dtemp
+ ad='(ad?ad:(1.3e-6*w))' pd='(pd?pd:2*(6.5e-7+w))' as='(as?as:(1.3e-6*w))' ps='(ps?ps:2*(6.5e-7+w))'
.ends p
*==================================================
*===============<< 5VGS/5VDS Isolation PMOS >>=====
*==================================================
.subckt pchi d g s b l=20u w=20u dtemp=0 ad=0 as=0 pd=0 ps=0 area_bd=0 pj_bd=0
mcore2 d g s b pch_core w='w' l='l' m=1 dtemp=dtemp
+ ad='(ad?ad:(1.3e-6*w))' pd='(pd?pd:2*(6.5e-7+w))' as='(as?as:(1.3e-6*w))' ps='(ps?ps:2*(6.5e-7+w))'         
dio_body psub b nbldio_core m=1 dtemp=dtemp
+ area='(area_bd?area_bd:((1e-5+w)*(l+1e-5)))'  pj='(pj_bd?pj_bd:(2*(w+l+2e-5)))'
.ends pchi
.lib 'cb040sp002.l' MOS_CORE
.endl MOS
*
.LIB MA5G40D
*==================================================
*=====<<Macro model of 5VGS/40VDS LDNMOS >>========
*==================================================
.subckt hvan d g s  w=1e-6 l=1e-6 dtemp=0 ad=0 pd=0 as=0 ps=0 area_bd=0 pj_bd=0
.param
RDLIN D n1 '1e-3+drdsw_5vn*(((min(1.2,2.16e-6/l))/(1+max(0,V(g,s))))**1)*((4.66e4+(224/(2.49e-6+w)))*(1+4e-3*(temper-25+dtemp)))*(-tanh(3)+tanh(((max(0,V(d,s))/(L+(70*(1+2e-3*(temper-25+dtemp)))))**1.5)+3))'
mcore n1 g s s an5401 w='w' l='l' dtemp=dtemp m=1
+ ad='(ad?ad:(w*(l+1.9e-6)))'          pd='(pd?pd:(2*(w+l+1.9e-6)))'
+ as='(as?as:0)'                       ps='(ps?ps:0)'
*
dio_body psub d hnwdio_core dtemp=dtemp m=1
+ area='(area_bd?area_bd:((8e-6+w)*(l+1.39e-5)))'  pj='(pj_bd?pj_bd:(2*(w+l+8e-6+1.39e-5)))'
rpsub psub 0 0.1
.ends hvan
*==================================================
*=====<<Macro model of 5VGS/40VDS LDPMOS >>========
*==================================================
.subckt hvap d g s   iso w=1e-6 l=1e-6 dtemp=0 ad=0 pd=0 as=0 ps=0 area_bd=0 pj_bd=0 area_iso=0 pj_iso=0
.param
rdlin d d1 'drdsw_5vp*(MAX(1E-4,(1E-3+2100*(TANH(((1e-5/W)*4.8e-2)*(MAX(0,(V(S,D)**1.3)*(1-((1e-5/W)*(-1e-3))*(temper-25+dtemp)))))))))'
mcore d1 g s s ap5401 w=w l=l m=1 dtemp=dtemp
+ as='(as?as:0)' ps='(ps?ps:0)' ad='(ad?ad:(w*(l+1.9e-6)))' pd='(pd?pd:(2*(w+l+1.9e-6)))'
dhpw_nbl d iso hpwdio_core m=1 dtemp=dtemp
+ area='(area_bd?area_bd:((w+1.2e-5)*(l+1.77e-5)))'  pj='(pj_bd?pj_bd:(2*((w+1.2e-5)+(l+1.77e-5))))'
dnbl_sub psub iso nbldio2_core m=1 dtemp=dtemp
+ area='(area_iso?area_iso:((w+3.2e-5)*(l+3.77e-5)))'  pj='(pj_iso?pj_iso:(2*((w+3.2e-5)+(l+3.77e-5))))'
rpsub psub 0 0.1
.ends hvap
.lib 'cb040sp002.l' MA5G40D_CORE
.ENDL MA5G40D
以下是NCH,PCH,AP5401,AN5401的模型参数.

yanzi123

LVS CMD:

;   LAYER DEFINITION
;   ================
*INPUT-LAYER
    NWELL           = 2         ;NW -- N-Well
    DIFF            = 3         ;Thin Oxide (OD)
    ;DIFF            = 11        + OD, used in VIS libraries
    ;DIFF            = 12        ;N+ OD, used in VIS libraries
    PIMP            = 7         P -- P+ S/D Implantation
    NIMP            = 8         ;NP -- N+ S/D Implantation
    POLY1           = 13        O -- Poly Si
    POLY2           = 14        ;P2 -- Poly 2
    CONT            = 15        ;CO -- Contact Window
    METAL1          = 16        ;M1 -- Metal-1
    VI1             = 17        ;Via1 Hole
    METAL2          = 18        ;M2 -- Metal-2
    VI2             = 27        ;Via2 Hole
    METAL3          = 28       ;M3 -- Metal-3
    VI3             = 29       ;Via3 Hole
    METAL4          = 31       ;M4 -- Metal-4
    PDD             = 21
    NDD             = 22
    PAD             = 19        ;CB -- Passivation Window
    ESD             = 30        ;ESD
    PSUB2           = 50        ;apply for subtract2 ground
    LRP2            = 93        ;LRP2 -- lower resistance poly2 resistor
    HVNW            = 99        ;HV-NWELL
    HVPW            = 116       ;HV-PWELL
    HVTN            = 142       ;HV-VT N imp ; HVOX logic
    NBL             = 179       ;N+ buried layer for SiGe BiCMOS process
    HVNW2           = 127       ;Asy DDD PMOS implant
    PSB             = 110       ;PSB implant for Asy LDNMOS source only
    NBODY           = 185
    PBODY           = 183
    BJTDUMY         = 49        ;BJT dummy mask
    RWDUMMY         = 52        ;N_well resistor dummy mask
    RPDUMMY         = 54        ;poly resistor dummy mask
    DIODE           = 56        ;dummy layer to form diode
    CDUMMY          = 68        ;dummy layer to form poly/m1/m2 cap.
    RMDUMMY         = 69        ;metal resistor dummy mask
    FIDUM1          = 115 DATATYPE 1
    FIDUM2          = 115 DATATYPE 2
    FIDUM4          = 115 DATATYPE 4
    FIDUM6          = 115 DATATYPE 6
    SUBSTRATE       = BULK 99
    TEXT 40 ATTACH MT1          ;Metal-1 text
    TEXT 41 ATTACH MT2          ;Metal-2 text
    TEXT 42 ATTACH MT3          ;Metal-3 text
    TEXT 43 ATTACH MT4          ;Metal-4 text
    CONNECT-LAYER   = BULK2 NXWELL PSUB HXNW HXNW2 NBL HXPW NBDY PBDY HVTN NTYPE PTYPE PNSHORT
    CONNECT-LAYER   = PDDPDIF PDIFF NDIFF
    CONNECT-LAYER   = CPOLY C2POLY MT1 MT2 MT3 MT4
*END


;   To form N_Well Resistor and N_Well
    AND RWDUMMY NWELL RWELL        ; N-well resistor layer
    NOT NWELL RWELL NXWELL         ; define N_well region
    SEL RPDUMMY OVERLAP DIFF DRDUM ; DIFF RESISTOR DUMMY
    NOT RPDUMMY DRDUM RP1
    SEL RP1 OVERLAP POLY1 P1RDUM   ; POLY1 RESISTOR DUMMY
    NOT RP1 P1RDUM RP2
    SEL RP2 OVERLAP POLY2 P2RDUM   ; POLY2 RESISTOR DUMMY
;   To form diff resistor
    AND DIFF DRDUM RESD       ; diff resistor layer
    AND RESD NIMP RESDN1      ; N+OD resistor
    NOT RESDN1 NBODY RESDN
    AND RESD PIMP RESDP       ; P+OD resistor
    NOT DIFF RESD MDIFF       ; diff region
;   To form poly1 resistor
    AND POLY1 P1RDUM RESP1   ; poly1 resistor
    NOT POLY1 RESP1 CPOLY    ; cpoly is for connection
    AND RESP1 PIMP RESPP     ; p+poly1 resistor
    NOT RESP1 RESPP RESPN    ; poly1 resistor
;   To form poly1/poly2 capacitor
    AND POLY1 POLY2 P1P2
    AND P1P2 LRP2 CAPPL
;    AND POLY1 POLY2 CAPPL  



;   P_SUBSTRATE TYPE DEFINITION
    NOT BULK HVNW2 N_HVNW2
    NOT BULK HVNW N_HVNW
    NOT BULK NWELL N_NW
   
    SEL N_HVNW2 INSIDE NBL BULK1A
    SEL N_HVNW INSIDE NBL BULK1B
    SEL N_NW INSIDE NBL BULK1C
    OR BULK1A BULK1B BULK1AB
    OR BULK1AB BULK1C BULK1
    OR NWELL HVNW N_WELL1
    OR N_WELL1 HVNW2 N_WELL
    OR N_WELL HVPW AWELL
    NOT BULK BULK1 BULK2
        
    OR BULK1 BULK2 PPSUB1
    NOT PPSUB1 AWELL PPSUB
    SIZE PSUB2 BY 0.025 PSUB2S
   
    AND PPSUB PSUB2 PSUB2A
    NOT PPSUB PSUB2S PSUB1
    OR PSUB1 PSUB2A PSUB
;   DEFINE GATE_TYPE
    AND CPOLY MDIFF GATE               ; define poly gate
    AND GATE PIMP PGATE1A
    NOT PGATE1A FIDUM1 PGATE1          ; define P+ gate
    SEL PGATE1 OUTSIDE BULK1A PGATE    ; define 5V PMOS
    SEL PGATE1 INSIDE BULK1A PGATEI1    ; define Isolated 5V PMOS
    AND PGATEI1 FIDUM4 PGATEI
    AND GATE NIMP NGATE1A
    NOT NGATE1A FIDUM1 NGATE1          ; define N+ gate
    NOT NGATE1 ESD NGATE2
    SEL NGATE2 OUTSIDE BULK1A NGATE

;   DEFINE P/N SOURCE/DRAIN REGION
    NOT PTHIN GATE PDIFF  ; define P+ s/d region
    NOT NTHIN GATE NDIFF  ; define N+ s/d region

yanzi123

;   ----------
    ELEMENT MOS[N] NGATE CPOLY NDIFF PSUB           ; nch ; define nmos in p_sub
    ELEMENT MOS[P] PGATE CPOLY PDIFF NXWELL         ; pch ; define pmos in n_well

因为CMD很长,就不粘贴出来了,

上面部分的LVS,CMD,包含了普通MOS的定义.但是我画出来的NMOS,PMOS居然识别不了,不知道该怎么办

highcao2004

you can load the .DAT file to your dracula interactive to check if the generated layers listed in the element command are all there, then one by one,
whether or not they are right as you imaged,then,
you can find the rootcause...good luck!

yanzi123

谢谢前辈!我试下

yanzi123

但是怎么LOAD .DAT文件呢?