library compiler建DFF cell的疑问

red_0220

各位好，小弟打算跑HSPICE改变一下cell library的资料
但有部分还是不太理解，以下是D-Flip Flop(DFF)接脚D及CLK部分

  pin(D) {
    nextstate_type : data;
    direction : input ;
    capacitance : 0.001165;
    internal_power() {
      when : "!CK";
      power(POWER_7x1) {
        index_1("0.009652,0.016106,0.025992,0.046675,0.088958,0.216628,0.447814");
        values("0.003651,0.003635,0.003626,0.003611,0.003614,0.003725,0.004117");
      }
    }

values值是指不同的D端电容(index_1)在CLK=0时的POWER值吗?

    internal_power() {
      when : "CK";
      power(POWER_7x1) {
        index_1("0.009645,0.016106,0.025991,0.046674,0.088957,0.216628,0.447814");
        values("0.000127,0.000122,0.000120,0.000119,0.000117,0.000116,0.000114");
      }
    }
    timing() {
      related_pin : "CK";
      sdf_edges   : both_edges;
      timing_type : setup_rising;
      rise_constraint(CONST_3x3) {
        index_1("0.006000,0.217000,0.434000");
        index_2("0.006000,0.108000,0.217000");
        values("0.029659,0.026470,0.036963",\
               "0.032032,0.023912,0.031939",\
               "0.004917,0.000010,0.004825");
      }

values是指DATA输入transition time(index_1)跟CLK输入transition time(index_2)不同时所得到的setup timing吗?

  fall_constraint(CONST_3x3) {
        index_1("0.006000,0.217000,0.434000");
        index_2("0.006000,0.108000,0.217000");
        values("0.074043,0.058526,0.059156",\
               "0.152860,0.139810,0.137970",\
               "0.231770,0.216260,0.216890");
      }
    }

timing() {
      related_pin : "CK";
      sdf_edges   : both_edges;
      timing_type : hold_rising;
      rise_constraint(CONST_3x3) {
        index_1("0.006000,0.217000,0.434000");
        index_2("0.006000,0.108000,0.217000");
        values("-0.005932,-0.005209,-0.015703",\
               "0.013887,0.014610,0.004117",\
               "0.060728,0.056519,0.043560");
      }
      fall_constraint(CONST_3x3) {
        index_1("0.006000,0.217000,0.434000");
        index_2("0.006000,0.108000,0.217000");
        values("-0.018261,-0.002744,-0.005839",\
               "-0.028829,-0.021521,-0.028745",\
               "-0.004426,0.053203,-0.004342");
      }
    }
  }
  pin(CK) {
    direction : input ;
    capacitance : 0.001915;
    max_transition : 0.217000;
    clock : true;
    internal_power() {
      power(POWER_7x1) {
        index_1("0.009651,0.016105,0.025992,0.046675,0.088957,0.216628,0.447814");
        values("0.004066,0.004029,0.004007,0.004000,0.004050,0.004346,0.005062");
      }
    }

values值是指不同的CLK端电容(index_1)在CLK=0时的POWER值吗?

min_pulse_width_high : 0.061268;
    min_pulse_width_low  : 0.125320;

CLK Hi/Low的长度?
  }
}


有观念误解的话希望帮忙修正..谢谢

xinfubin

kankank

coolwall

路过看看