Arithmetic Built-in Self-Test for Embedded Systems

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Contents
Preface vii
1 Built-in Self-Test 1
1.1 Introduction 1
1.2 Design for Testability 4
1.2.1 Controllability and Observability 4
1.2.2 Ad Hoc Techniques 6
1.2.3 Scan Designs 8
1.2.4 Boundary-Scan Architecture 12
1.2.5 Test Point Insertion 14
1.3 Generation of Test Vectors 17
1.3.1 Exhaustive Testing 17
1.3.2 Pseudo-Exhaustive Testing 17
1.3.3 Pseudo-Random Testing 19
1.3.4 Weighted Patterns 23
1.3.5 Reseeding of Linear Feedback Shift Registers 24
1.3.6 Diffraction 28
1.3.7 Pattern Mapping 30
1.3.8 Scan-Encoded Patterns 30
1.4 Compaction of Test Responses 32
1.4.1 Objectives and Requirements 32
1.4.2 Compaction Schemes 33
1.4.3 Error Models and Aliasing 35
1.5 BIST Schemes for Random Logic 38
1.5.1 Design Rules for BIST 38
1.5.2 Serial BIST Architectures 42
1.5.3 Parallel BIST Architectures 44
1.5.4 BIST controllers 47
1.5.5 Modular BIST 49
1.5.6 Automation of BIST 52
1.6 BIST for Memory Arrays 53
1.6.1 Schemes Based on Deterministic Tests 55
1.6.2 Pseudo-Random Testing 57
1.6.3 Transparent BIST 57
Generation of Test Vectors 61
2.1 Additive Generators of Exhaustive Patterns 61
2.1.1 Basic Notions 62
2.1.2 Optimal Generators for Single Size Subspaces 65
2.1.3 Operand Interleaving 70
2.1.4 The Best Generators for Subspaces Within a Range of Sizes 72
2.2 Other Generation Schemes 76
2.2.1 Emulation of LFSRs and CAs 76
2.2.2 Weighted Patterns . 77
2.2.3 Generators for Delay Testing 79
2.3 Two-Dimensional Generators 81
Test-Response Compaction 87
3.1 Binary Adders 88
3.2 l's Complement Adders 90
3.2.1 Steady State Analysis 90
3.2.2 Transient Behavior 93
3.2.3 Detection of Internal Faults 100
3.3 Rotate-Carry Adders 101
3.3.1 Fault-Free Operation . 102
3.3.2 Test-Response Compaction 104
3.3.3 The Compaction Quality 108
3.4 Cascaded Compaction Scheme 112
Fault Diagnosis 117
4.1 Analytical Model 117
4.2 Experimental Validation 121
4.3 The Quality of Diagnostic Resolution 122
4.4 Fault Diagnosis in Scan-Based Designs 126
5 BIST of Data-Path Kernel 135
5.1 Testing of ALU 135
5.1.1 Generation of Test Vectors 137
5.1.2 Test Application Phase 137
5.1.3 Compaction of Test Responses 139
5.1.4 Experimental Validation 139
5.2 Testing of the MAC Unit 140
5.3 Testing of the Microcontroller 141
6 Fault Grading 147
6.1 Fault Simulation Framework 148
6.2 Functional Fault Simulation 150
6.2.1 Ripple-Carry Adder 152
6.2.2 Subtracter 153
6.2.3 Carry-Lookahead Adder 153
6.2.4 Arithmetic and Logic Unit 154
6.2.5 Multiplexor 154
6.2.6 Array Multiplier 154
6.2.7 Booth Multiplier 159
6.3 Experimental Results 163
6.3.1 Performance of Building Block Models 164
6.3.2 High-Level Synthesis Benchmark Circuits 165
6.3.3 Comparison with PROOFS 166
7 High-Level Synthesis 173
7.1 Implementation-Dependent Fault Grading 174
7.1.1 Ripple-Carry Adder 174
7.1.2 Carry-Lookahead Adder 174
7.1.3 Carry-Skip Adder 175
7.2 Synthesis Steps 176
7.3 Simulation Results 178
8 ABIST at Work 185
8.1 Testing of Random Logic 185
8.1.1 Pseudo-Random Testing 185
8.1.2 Deterministic Testing 187
8.2 Memory Testing 192
8.2.1 Test program 192
8.2.2 Memory Array Faults 194
8.2.3 Read and Write Logic Faults 194
8.2.4 Address Decoder Faults 195
8.2.5 Multiple Faults 195
8.3 Digital Integrators 196
8.3.1 Testing of the Unmodified Integrator 197
8.3.2 Modified Integrator 199
8.3.3 Register File-Based Integrator 203
8.4 Leaking Integrators 207
8.4.1 Unidirectional Faults 209
8.4.2 Bidirectional Faults 215
8.4.3 An Improved Compaction Scheme 218
9 Epilog 223
A Tables of Generators 227
B Assembly Language 245
Bibliography 249
Index 265

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