VHDL语言的高手们帮忙来看一下吧

lincus

我们学校做硬件课程设计，一个异步，四进制加减计数器，代码如下：
-------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-------------------------------------------------------
ENTITY accounter IS
PORT(q:OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
   ud,clr,clk:IN STD_LOGIC);
END accounter;
-------------------------------------------------------
ARCHITECTURE accounter OF accounter IS
SIGNAL qn:STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL qn0,qn1:STD_LOGIC;
SIGNAL qbn0,qbn1:STD_LOGIC;
SIGNAL d0,d1:STD_LOGIC;
BEGIN
qn<=qn1&qn0;
q<="00" WHEN clr='0' ELSE qn;
d0<=qbn0;     --驱动方程
d1<=qbn1;
PROCESS(clr,clk,qn0,qbn0,ud)     --状态方程
BEGIN
  IF(ud='0') THEN     --加法计数
   IF(clk'EVENT AND clk='1') THEN
    qn0<=d0;
    qbn0<=NOT d0;
   END IF;
   IF(qbn0'EVENT AND qbn0='1') THEN
    qn1<=d1;
    qbn1<=NOT d1;
   END IF;
  ELSE     --减法计数
   IF(clk'EVENT AND clk='1') THEN
    qn0<=d0;
    qbn0<=NOT d0;
   END IF;
   IF(qn0'EVENT AND qn0='1') THEN
    qn1<=d1;
    qbn1<=NOT d1;
   END IF;
  END IF;
END PROCESS;
END accounter;
-------------------------------------------------------
全部综合信息：
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
Info: Processing started: Sat Aug 22 13:37:03 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off accounter -c accounter
Info: Found 2 design units, including 1 entities, in source file accounter.vhd
Info: Found design unit 1: accounter-accounter
Info: Found entity 1: accounter
Info: Elaborating entity "accounter" for the top level hierarchy
Error (10821): HDL error at accounter.vhd(22): can't infer register for "qbn1" because its behavior does not match any supported register model
Info (10041): Inferred latch for "qbn1" at accounter.vhd(20)
Error (10821): HDL error at accounter.vhd(22): can't infer register for "qn1" because its behavior does not match any supported register model
Info (10041): Inferred latch for "qn1" at accounter.vhd(20)
Error (10821): HDL error at accounter.vhd(22): can't infer register for "qbn0" because its behavior does not match any supported register model
Info (10041): Inferred latch for "qbn0" at accounter.vhd(20)
Error (10821): HDL error at accounter.vhd(22): can't infer register for "qn0" because its behavior does not match any supported register model
Info (10041): Inferred latch for "qn0" at accounter.vhd(20)
Error (10822): HDL error at accounter.vhd(23): couldn't implement registers for assignments on this clock edge
Error (10822): HDL error at accounter.vhd(27): couldn't implement registers for assignments on this clock edge
Error (10822): HDL error at accounter.vhd(32): couldn't implement registers for assignments on this clock edge
Error (10822): HDL error at accounter.vhd(36): couldn't implement registers for assignments on this clock edge
Error: Can't elaborate top-level user hierarchy
Error: Quartus II Analysis & Synthesis was unsuccessful. 9 errors, 0 warnings
Error: Peak virtual memory: 186 megabytes
Error: Processing ended: Sat Aug 22 13:37:05 2009
Error: Elapsed time: 00:00:02
Error: Total CPU time (on all processors): 00:00:02
请问应该如何解决？
Quartus II 5中就可以通过编译，9.0中就不行，高手们来帮帮我吧！

equalizer

同一个process里有多个时钟信号（clk，qbn，qn0），这种代码风格就不是好的可综合的RTL。

楼主一定要设计成异步电路吗？同步电路写起来更简单，时序分析什么的也更好掌握。

整个代码看起来很混乱。比如：clr在process里根本没用到，却写在了敏感列表里。qn0和qbn0的表达式在加法和减法时都一样。

楼主确定代码的功能正确吗？

williamloo

寄存器声明的问题。

patriotiii

xuexi