【2008 Springer】Timing Optimization Through Clock Skew Scheduling

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by   Ivan S. Kourtev
                  
              Ivan S. Kourtev                            (Author)       
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(Author), Baris Taskin (Author), Eby G. Friedman (Author)
                Key Phrases: clock skew scheduling, skew scheduling problem, local data path, Springer Science, Business Media, Timing Properties of Synchronous Systems (more...)

Editorial Reviews        Product Description
Thefocus of this book is on timing analysis and optimization techniquesfor circuits with level-sensitive memory elements (registers).Level-sensitive registers are becoming significantly more popular inpractice as integrated circuit densities are increasing and the'performance-per-power' metric for integrated circuits becomes a keyissue. Therefore, techniques for understanding level-sensitive basedcircuits and for optimizing the performance of such circuits areincreasingly important. The book includes the following major topics inthe timing analysis and optimization of level-sensitive circuits. Alinear programming (LP) formulation applicable to the timing analysisof large scale circuits. The formulation uses a variation of the big Mmethod - called the modified big M method - to transform the non-linearconstraints in the problem formulation into solvable linearconstraints.This LP formulation is computationally efficient anddemonstrates significant circuit performance improvement. By makingmaximum use of cycle stealing, operation at a higher clock frequency(reduced clock period) is possible. A delay insertion methodology thatimproves the efficiency of clock skew scheduling in level-sensitivecircuits. It is shown that re-convergent paths limit the improvement ofcircuit performance that can be achieved through clock skew scheduling.The described delay insertion method mitigates the limitations cause byre-convergent data paths and improves the results of timingoptimization (for increased clock frequency). A summary of circuitpartitioning, placement and synchronization methodologies that enablesthe implementation of high speed, low power circuits synchronized withultra modern resonant clocking technology (such as travelingoscillators/waves).The described framework includes the particularcircuit partitioning and placement methodologies that permit thehierarchical application of non-zero clock skew system timing inresonant clocking based circuits. A framework for and results fromimplementing the described timing optimization algorithms in a parallelcomputing environment. As multi-core microprocessors becomecommonplace, computationally intense algorithms can benefit greatly byexploiting this available parallelism. The framework uses a heuristicapproach to generate circuit partition and solve them independently onprocessors/computers working on parallel. This is one of the first suchapplications of explicit parallelism in Electronic Design Automation(EDA), and, will be of great interest to practicing EDA engineers.

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