我用的是Verilog
我在设计一个流水结构的模块时,必须使用一些常数。我发现他们的存在对设计的速度居然有很大影响!我使用的方法是:1,直接写数字,这样做综合的结果是把‘1’与高电压连接起来;把‘0’与地连在一起,综合的关键路径是30ns。2,使用DFF把这些常数先存起来,写法是:always@(posedge clk)
begin
cons1<=13'b0101010101001;
end
这样的综合结果是关键路径20ns。
现在很迷惑,不知道如何处理这些信源。
the improvement is probably caused by the introduction of extra flip-flops.
synthesis tools may do retiming to balance the combinatorial delay among
flip-flops.
you can verify it by not registering the first stage (constant), but registering at the second stage and see whether you see the same timing improvement or not. synthesis tool also reports retiming done.
there shall be nothing to do with the constant.