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楼主 |
发表于 2004-5-19 13:45:08
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紧急求助!急啊!帮忙看以下程序啊
再请问:
匹配滤波器程序如下:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity mf is
generic(
iIndatawidth : integer:=8;
ioutdatawidth : integer:=16;
ioversamplerate :integer:=16;
inumofchips :integer:=128
);
port(
incode :in std_logic;
indata :in std_logic_vector (iIndatawidth-1 downto 0);
sysclk : in std_logic;
sysrst : in std_logic;
result ut std_logic_vector (ioutdatawidth-1 downto 0)
);
end mf;
architecture virtex of mf is
type resultarray is array (inumofchips-1 downto 0)
of std_logic_vector(ioutdatawidth-1 downto 0);
signal zero :std_logic_vector(ioutdatawidth-1 downto 0);
signal loutcode :std_logic_vector(inumofchips-1 downto 0);
signal lresult :resultarray;
component mf_parallel_tap
generic(
iIndatawidth :integer :=8;
ioutdatawidth :integer :=16;
ioversamplerate : integer :=16
);
port(
incode :in std_logic;
indata :in std_logic_vector(iIndatawidth-1 downto 0);
prevtap :in std_logic_vector(ioutdatawidth-1 downto 0);
sysclk :in std_logic;
sysrst :in std_logic;
outcode ut std_logic;
result ut std_logic_vector(ioutdatawidth-1 downto 0)
);
end component;
begin
zero<=(others=>'0');
firsttap : mf_parallel_tap
generic map(
iIndatawidth =>iIndatawidth,
ioutdatawidth=>ioutdatawidth,
ioversamplerate=>ioversamplerate
)
port map(
incode =>incode,
indata=>indata,
prevtap =>zero,
sysclk =>sysclk,
sysrst =>sysrst,
outcode =>loutcode(0),
result => lresult(0)
);
InstTaps: for I in 1 to inumofchips-1 generate
Taps :mf_parallel_tap
generic map(
iIndatawidth =>iIndatawidth,
ioutdatawidth =>ioutdatawidth,
ioversamplerate=>ioversamplerate
)
port map(
Incode => loutcode(I-1),
Indata=> Indata,
Prevtap =>lresult(I-1),
sysclk => sysclk,
sysrst =>sysrst,
outcode => loutcode(I),
result =>lresult(I)
);
end generate InstTaps;
Generateresult : Result<=lResult(inumofchips-1);
end virtex;
在编译时:当inumofchips=128时,编译的进度条走了一点一就停住了。也不报错,也不能通过。
当inumofchips=16时就能通过
在波形仿真时,输出为0。
请问,这是为什么?多谢!
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