信号边沿检测

awetman

//边沿检测模块,要求signal保持时间在一个clock周期以上
module egde_check(clock,signal,rising_flag,falling_flag);
input clock;
input signal;
output rising_flag;
output falling_flag;
reg [2:0] temp=3'b000;
always @(posedge clock)
begin
  temp<={temp[1:0],signal};
end
assign rising_flag=(temp[1:0]==2'b01)?1'b1:1'b0;
assign falling_flag=(temp[1:0]==2'b10)?1'b1:1'b0;
endmodule
//testbench
module test_edge_check_v;
// Inputs
reg clock;
reg signal;
// Outputs
wire rising_flag;
wire falling_flag;
// Instantiate the Unit Under Test (UUT)
egde_check uut (
  .clock(clock),
  .signal(signal),
  .rising_flag(rising_flag),
  .falling_flag(falling_flag)
);
initial begin
  // Initialize Inputs
  clock = 0;
  signal = 0;
  // Wait 100 ns for global reset to finish
  #100;
        
  // Add stimulus here
  signal=1;
  #500;
  signal=0;
  #500;
  signal=1;
  #200;
  signal=0;
  #100;
  signal=1;
  #300;
  signal=0;
end
   always #100 clock=~clock   ;     
endmodule