|
|
马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。
您需要 登录 才可以下载或查看，没有账号？注册
x
Designing Reliable and Efficient Networks on ChipsSeries: Lecture Notes in Electrical Engineering , Vol. 34
Murali, Srinivasan
2009, X, 198 p., Hardcover
ISBN: 978-1-4020-9756-0
About this book
Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another important design challenge for NoCs will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. The purpose of Designing Reliable and Efficient Networks on Chips is to provide state-of-the-art methods to solve some of the most important and time-intensive problems encountered during NoC design.
Written for:
System level architects and designers, communication architecture/interconnect designers, design automation engineers, also of general interest to designers working in related fields, such as sensor, body area and automotive networks
Keywords:
- Design
- Networks on Chips
- Reliability
- Systems on Chips
|
|
/1 
eetop公众号
创芯大讲堂
创芯人才网
发表于 2009-5-28 15:10:35
