谁能救救俺！？

tjpu_wenyanbin

Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 8.1 Build 163 10/28/2008 SJ Web Edition
Info: Processing started: Wed May 20 20:27:36 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lcd -c lcd
Info: Found 1 design units, including 1 entities, in source file clklogic.gdf
Info: Found entity 1: clklogic
Info: Found 2 design units, including 1 entities, in source file lcd.vhd
Info: Found design unit 1: lcd-Behavioral
Info: Found entity 1: lcd
Info: Found 2 design units, including 1 entities, in source file char_ram.vhd
Info: Found design unit 1: char_ram-fun
Info: Found entity 1: char_ram
Info: Found 2 design units, including 1 entities, in source file rp.vhd
Info: Found design unit 1: rp-Behavioral
Info: Found entity 1: rp
Warning: Can't analyze file -- file E:/sr/CPLD/lcd/clkin.vhd is missing
Info: Found 2 design units, including 1 entities, in source file clkn.vhd
Info: Found design unit 1: clkn-Behavioral
Info: Found entity 1: clkn
Info: Elaborating entity "lcd" for the top level hierarchy
Info: Elaborating entity "rp" for hierarchy "rp:aa"
Info: Elaborating entity "clkn" for hierarchy "rp:aa|clkn:aa"
Warning (10492): VHDL Process Statement warning at clkn.vhd(27): signal "clk_out" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Info: Inferred 8 megafunctions from design logic
Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "rp:aa|Div1"
Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "rp:aa|Div3"
Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "rp:aa|Div4"
Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "rp:aa|Div0"
Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "rp:aa|Mod0"
Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "rp:aa|Div2"
Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "rp:aa|Mod1"
Info: Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "rp:aa|Mod2"
Info: Elaborated megafunction instantiation "rp:aa|lpm_divideiv1"
Info: Instantiated megafunction "rp:aa|lpm_divideiv1" with the following parameter:
Info: Parameter "LPM_WIDTHN" = "23"
Info: Parameter "LPM_WIDTHD" = "11"
Info: Parameter "LPM_NREPRESENTATION" = "SIGNED"
Info: Parameter "LPM_DREPRESENTATION" = "SIGNED"
Info: Parameter "LPM_HINT" = "LPM_REMAINDERPOSITIVE=FALSE"
Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_dgo.tdf
Info: Found entity 1: lpm_divide_dgo
Info: Found 1 design units, including 1 entities, in source file db/abs_divider_1dg.tdf
Info: Found entity 1: abs_divider_1dg
Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_7oe.tdf
Info: Found entity 1: alt_u_div_7oe
Info: Found 1 design units, including 1 entities, in source file db/add_sub_e7c.tdf
Info: Found entity 1: add_sub_e7c
Info: Found 1 design units, including 1 entities, in source file db/add_sub_f7c.tdf
Info: Found entity 1: add_sub_f7c
Info: Found 1 design units, including 1 entities, in source file db/add_sub_v8c.tdf
Info: Found entity 1: add_sub_v8c
Info: Found 1 design units, including 1 entities, in source file db/add_sub_09c.tdf
Info: Found entity 1: add_sub_09c
Info: Found 1 design units, including 1 entities, in source file db/add_sub_g7c.tdf
Info: Found entity 1: add_sub_g7c
Info: Found 1 design units, including 1 entities, in source file db/add_sub_h7c.tdf
Info: Found entity 1: add_sub_h7c
Info: Found 1 design units, including 1 entities, in source file db/add_sub_i7c.tdf
Info: Found entity 1: add_sub_i7c
Info: Found 1 design units, including 1 entities, in source file db/add_sub_j7c.tdf
Info: Found entity 1: add_sub_j7c
Info: Found 1 design units, including 1 entities, in source file db/add_sub_k7c.tdf
Info: Found entity 1: add_sub_k7c
Info: Found 1 design units, including 1 entities, in source file db/add_sub_l7c.tdf
Info: Found entity 1: add_sub_l7c
Info: Found 1 design units, including 1 entities, in source file db/add_sub_m7c.tdf
Info: Found entity 1: add_sub_m7c
Info: Found 1 design units, including 1 entities, in source file db/add_sub_u8c.tdf
Info: Found entity 1: add_sub_u8c
Info: Found 1 design units, including 1 entities, in source file db/lpm_abs_me9.tdf
Info: Found entity 1: lpm_abs_me9
Info: Found 1 design units, including 1 entities, in source file db/lpm_abs_pe9.tdf
Info: Found entity 1: lpm_abs_pe9
Info: Found 1 design units, including 1 entities, in source file db/add_sub_p0f.tdf
Info: Found entity 1: add_sub_p0f
Info: Found 1 design units, including 1 entities, in source file db/add_sub_m0f.tdf
Info: Found entity 1: add_sub_m0f
Info: Elaborated megafunction instantiation "rp:aa|lpm_divideiv3"
Info: Instantiated megafunction "rp:aa|lpm_divide:Div3" with the following parameter:
Info: Parameter "LPM_WIDTHN" = "23"
Info: Parameter "LPM_WIDTHD" = "8"
Info: Parameter "LPM_NREPRESENTATION" = "SIGNED"
Info: Parameter "LPM_DREPRESENTATION" = "SIGNED"
Info: Parameter "LPM_HINT" = "LPM_REMAINDERPOSITIVE=FALSE"
Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_3fo.tdf
Info: Found entity 1: lpm_divide_3fo
Info: Found 1 design units, including 1 entities, in source file db/abs_divider_nbg.tdf
Info: Found entity 1: abs_divider_nbg
Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_jle.tdf
Info: Found entity 1: alt_u_div_jle
Info: Found 1 design units, including 1 entities, in source file db/lpm_abs_cd9.tdf
Info: Found entity 1: lpm_abs_cd9
Info: Found 1 design units, including 1 entities, in source file db/add_sub_cve.tdf
Info: Found entity 1: add_sub_cve
Info: Elaborated megafunction instantiation "rp:aa|lpm_divide:Div4"
Info: Instantiated megafunction "rp:aa|lpm_divide:Div4" with the following parameter:
Info: Parameter "LPM_WIDTHN" = "23"
Info: Parameter "LPM_WIDTHD" = "5"
Info: Parameter "LPM_NREPRESENTATION" = "SIGNED"
Info: Parameter "LPM_DREPRESENTATION" = "SIGNED"
Info: Parameter "LPM_HINT" = "LPM_REMAINDERPOSITIVE=FALSE"
Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_0fo.tdf
Info: Found entity 1: lpm_divide_0fo
Info: Found 1 design units, including 1 entities, in source file db/abs_divider_kbg.tdf
Info: Found entity 1: abs_divider_kbg
Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_dle.tdf
Info: Found entity 1: alt_u_div_dle
Info: Found 1 design units, including 1 entities, in source file db/lpm_abs_9d9.tdf
Info: Found entity 1: lpm_abs_9d9
Info: Found 1 design units, including 1 entities, in source file db/add_sub_9ve.tdf
Info: Found entity 1: add_sub_9ve
Info: Elaborated megafunction instantiation "rp:aa|lpm_divide:Div0"
Info: Instantiated megafunction "rp:aa|lpm_divide:Div0" with the following parameter:
Info: Parameter "LPM_WIDTHN" = "32"
Info: Parameter "LPM_WIDTHD" = "8"
Info: Parameter "LPM_NREPRESENTATION" = "SIGNED"
Info: Parameter "LPM_DREPRESENTATION" = "SIGNED"
Info: Parameter "LPM_HINT" = "LPM_REMAINDERPOSITIVE=FALSE"
Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_4fo.tdf
Info: Found entity 1: lpm_divide_4fo
Info: Found 1 design units, including 1 entities, in source file db/abs_divider_obg.tdf
Info: Found entity 1: abs_divider_obg
Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_kle.tdf
Info: Found entity 1: alt_u_div_kle
Info: Found 1 design units, including 1 entities, in source file db/lpm_abs_qe9.tdf
Info: Found entity 1: lpm_abs_qe9
Info: Found 1 design units, including 1 entities, in source file db/add_sub_q0f.tdf
Info: Found entity 1: add_sub_q0f
Info: Elaborated megafunction instantiation "rp:aa|lpm_divide:Mod0"
Info: Instantiated megafunction "rp:aa|lpm_divide:Mod0" with the following parameter:
Info: Parameter "LPM_WIDTHN" = "33"
Info: Parameter "LPM_WIDTHD" = "32"
Info: Parameter "LPM_NREPRESENTATION" = "UNSIGNED"
Info: Parameter "LPM_DREPRESENTATION" = "UNSIGNED"
Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_sql.tdf
Info: Found entity 1: lpm_divide_sql
Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_anh.tdf
Info: Found entity 1: sign_div_unsign_anh
Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_foe.tdf
Info: Found entity 1: alt_u_div_foe
Info: Found 1 design units, including 1 entities, in source file db/add_sub_19c.tdf
Info: Found entity 1: add_sub_19c
Info: Found 1 design units, including 1 entities, in source file db/add_sub_29c.tdf
Info: Found entity 1: add_sub_29c
Info: Found 1 design units, including 1 entities, in source file db/add_sub_39c.tdf
Info: Found entity 1: add_sub_39c
Info: Found 1 design units, including 1 entities, in source file db/add_sub_49c.tdf
Info: Found entity 1: add_sub_49c
Info: Found 1 design units, including 1 entities, in source file db/add_sub_59c.tdf
Info: Found entity 1: add_sub_59c
Info: Found 1 design units, including 1 entities, in source file db/add_sub_69c.tdf
Info: Found entity 1: add_sub_69c
Info: Found 1 design units, including 1 entities, in source file db/add_sub_79c.tdf
Info: Found entity 1: add_sub_79c
Info: Found 1 design units, including 1 entities, in source file db/add_sub_89c.tdf
Info: Found entity 1: add_sub_89c
Info: Found 1 design units, including 1 entities, in source file db/add_sub_99c.tdf
Info: Found entity 1: add_sub_99c
Info: Found 1 design units, including 1 entities, in source file db/add_sub_a9c.tdf
Info: Found entity 1: add_sub_a9c
Info: Found 1 design units, including 1 entities, in source file db/add_sub_b9c.tdf
Info: Found entity 1: add_sub_b9c
Info: Found 1 design units, including 1 entities, in source file db/add_sub_c9c.tdf
Info: Found entity 1: add_sub_c9c
Info: Found 1 design units, including 1 entities, in source file db/add_sub_d9c.tdf
Info: Found entity 1: add_sub_d9c
Info: Found 1 design units, including 1 entities, in source file db/add_sub_e9c.tdf
Info: Found entity 1: add_sub_e9c
Info: Found 1 design units, including 1 entities, in source file db/add_sub_f9c.tdf
Info: Found entity 1: add_sub_f9c
Info: Found 1 design units, including 1 entities, in source file db/add_sub_g9c.tdf
Info: Found entity 1: add_sub_g9c
Info: Found 1 design units, including 1 entities, in source file db/add_sub_h9c.tdf
Info: Found entity 1: add_sub_h9c
Info: Found 1 design units, including 1 entities, in source file db/add_sub_i9c.tdf
Info: Found entity 1: add_sub_i9c
Info: Found 1 design units, including 1 entities, in source file db/add_sub_j9c.tdf
Info: Found entity 1: add_sub_j9c
Info: Found 1 design units, including 1 entities, in source file db/add_sub_k9c.tdf
Info: Found entity 1: add_sub_k9c
Info: Found 1 design units, including 1 entities, in source file db/add_sub_l9c.tdf
Info: Found entity 1: add_sub_l9c
Info: Elaborated megafunction instantiation "rp:aa|lpm_divide:Div2"
Info: Instantiated megafunction "rp:aa|lpm_divide:Div2" with the following parameter:
Info: Parameter "LPM_WIDTHN" = "26"
Info: Parameter "LPM_WIDTHD" = "5"
Info: Parameter "LPM_NREPRESENTATION" = "SIGNED"
Info: Parameter "LPM_DREPRESENTATION" = "SIGNED"
Info: Parameter "LPM_HINT" = "LPM_REMAINDERPOSITIVE=FALSE"
Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_5fo.tdf
Info: Found entity 1: lpm_divide_5fo
Info: Found 1 design units, including 1 entities, in source file db/abs_divider_pbg.tdf
Info: Found entity 1: abs_divider_pbg
Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_lle.tdf
Info: Found entity 1: alt_u_div_lle
Info: Found 1 design units, including 1 entities, in source file db/lpm_abs_se9.tdf
Info: Found entity 1: lpm_abs_se9
Info: Found 1 design units, including 1 entities, in source file db/add_sub_s0f.tdf
Info: Found entity 1: add_sub_s0f
Info: Elaborated megafunction instantiation "rp:aa|lpm_divide:Mod1"
Info: Instantiated megafunction "rp:aa|lpm_divide:Mod1" with the following parameter:
Info: Parameter "LPM_WIDTHN" = "27"
Info: Parameter "LPM_WIDTHD" = "26"
Info: Parameter "LPM_NREPRESENTATION" = "UNSIGNED"
Info: Parameter "LPM_DREPRESENTATION" = "UNSIGNED"
Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_2rl.tdf
Info: Found entity 1: lpm_divide_2rl
Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_gnh.tdf
Info: Found entity 1: sign_div_unsign_gnh
Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_roe.tdf
Info: Found entity 1: alt_u_div_roe
Info: Elaborated megafunction instantiation "rp:aa|lpm_divide:Mod2"
Info: Instantiated megafunction "rp:aa|lpm_divide:Mod2" with the following parameter:
Info: Parameter "LPM_WIDTHN" = "24"
Info: Parameter "LPM_WIDTHD" = "23"
Info: Parameter "LPM_NREPRESENTATION" = "UNSIGNED"
Info: Parameter "LPM_DREPRESENTATION" = "UNSIGNED"
Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_tql.tdf
Info: Found entity 1: lpm_divide_tql
Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_bnh.tdf
Info: Found entity 1: sign_div_unsign_bnh
Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_goe.tdf
Info: Found entity 1: alt_u_div_goe
Info: 2 registers lost all their fanouts during netlist optimizations. The first 2 are displayed below.
Info: Register "rp:aa|m[30]" lost all its fanouts during netlist optimizations.
Info: Register "rp:aa|m[31]" lost all its fanouts during netlist optimizations.
Warning: Design contains 4 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "clkin"
Warning (15610): No output dependent on input pin "k2"
Warning (15610): No output dependent on input pin "k3"
Warning (15610): No output dependent on input pin "k4"
Info: Implemented 6813 device resources after synthesis - the final resource count might be different
Info: Implemented 7 input pins
Info: Implemented 12 output pins
Info: Implemented 6794 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 7 warnings
Info: Peak virtual memory: 252 megabytes
Info: Processing ended: Wed May 20 20:28:33 2009
Info: Elapsed time: 00:00:57
Info: Total CPU time (on all processors): 00:00:52
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 8.1 Build 163 10/28/2008 SJ Web Edition
Info: Processing started: Wed May 20 20:28:34 2009
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off lcd -c lcd
Info: Selected device EPM240T100C5 for design "lcd"
Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
Warning: Feature LogicLock is not available with your current license
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info: Device EPM240T100I5 is compatible
Info: Device EPM240T100A5 is compatible
Info: Device EPM570T100C5 is compatible
Info: Device EPM570T100I5 is compatible
Info: Device EPM570T100A5 is compatible
Warning: No exact pin location assignment(s) for 1 pins of 19 total pins
Info: Pin clk_out not assigned to an exact location on the device
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1000 MHz
Info: Assuming a global tsu requirement of 2.0 ns
Info: Assuming a global tco requirement of 1.0 ns
Info: Assuming a global tpd requirement of 1.0 ns
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN 12
Info: Automatically promoted some destinations of signal "rp:aa|jsen" to use Global clock
Info: Destination "rp:aa|jsen" may be non-global or may not use global clock
Info: Destination "rp:aa|m[22]" may be non-global or may not use global clock
Info: Destination "rp:aa|m[19]" may be non-global or may not use global clock
Info: Destination "rp:aa|m[18]" may be non-global or may not use global clock
Info: Destination "rp:aa|m[17]" may be non-global or may not use global clock
Info: Destination "rp:aa|m[16]" may be non-global or may not use global clock
Info: Destination "rp:aa|m[15]" may be non-global or may not use global clock
Info: Destination "rp:aa|m[14]" may be non-global or may not use global clock
Info: Destination "rp:aa|m[21]" may be non-global or may not use global clock
Info: Destination "rp:aa|m[20]" may be non-global or may not use global clock
Info: Limited to 10 non-global destinations
Info: Automatically promoted some destinations of signal "rp:aa|clk_out" to use Global clock
Info: Destination "rp:aa|clk_out" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "rp:aa|clkn:aa|clk_out" to use Global clock
Info: Destination "rp:aa|clkn:aa|clk_out" may be non-global or may not use global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
Info: Number of I/O pins in group: 1 (unused VREF, 3.3V VCCIO, 0 input, 1 output, 0 bidirectional)
  Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
Info: Statistics of I/O banks
  Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 6 total pin(s) used --  32 pins available
  Info: I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 12 total pin(s) used --  30 pins available
Info: Fitter preparation operations ending: elapsed time is 00:00:05
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter cannot place all nodes on current device -- Fitter will automatically make another fitting attempt and tightly pack logic elements
Info: Starting register packing
Info: Fitter is using Minimize Area packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing
Info: Fitter preparation operations ending: elapsed time is 00:00:01
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter cannot place all nodes on current device -- Fitter will automatically make another fitting attempt and tightly pack logic elements
Info: Starting register packing
Info: Fitter is using Minimize Area with Chains packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing
Info: Fitter preparation operations ending: elapsed time is 00:00:01
Info: Fitter placement preparation operations beginning
Error: Design contains 6638 blocks of type logic cell.  However, device contains only 240.
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Error: Can't fit design in device
Error: Quartus II Fitter was unsuccessful. 2 errors, 2 warnings
Error: Peak virtual memory: 185 megabytes
Error: Processing ended: Wed May 20 20:28:47 2009
Error: Elapsed time: 00:00:13
Error: Total CPU time (on all processors): 00:00:11
Error: Quartus II Full Compilation was unsuccessful. 4 errors, 9 warnings

tjpu_wenyanbin

最近在忙于毕设，用cpld驱动1602显示开关磁阻电机的转速，功率，电压，电流，转矩等参数。

显示部分我已经搞定，就是在调用元件  rp （用来计算转速，功率）和 clkn （转速模拟输入脉冲） 时出现如上情况：

不懂，提问如下，望有志之士帮忙！！谢谢！请批评指教，最关键还是指教！！

1）Error: Design contains 6638 blocks of type logic cell.  However, device contains only 240.（即上面红字最后一句）

      什么是logic cell ？

2）Info: Elaborated megafunction instantiation "rp:aa|lpm_divide:Mod1"  （其余红字部分摘一个）

      lpm_divide:mod0,1,2,以及lpm_divide:div0,1,2,3又是什么东西？为什么会占用那么多logic cell?

3）Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_dgo.tdf

      tdf是什么文件，用txt打开过，一点都看不懂！

4）最重要的一个问题，我用的是epm240t100c5，程序该改动哪一部分？还能往下做吗？

     注：程序编译时analysis&synthesis可以过去！下一步，fitter 出现上述问题。

zerowel

INFO 不用管它的，只是quartus对于warning的一些提示而已。

最关键的是那个Error:Design contains 6638 blocks of type logic cell.  However, device contains only 240.

你去看看下你的FPGA资源占用率是多少？

可能是你所用的Altera的FPGA芯片门数不够，导致布线工具根本无法完成布线。估计换个大点的FPGA芯片就好了吧

liulanghan

同意楼上的，你的设计需要6638个逻辑单元，而你选择的器件只有240个，所以设计不成功。。。。。。
另外，TDF文件是QUARTUS的代码文本文件，TXT打开看不出来设计的内容。。。。。。

tjpu_wenyanbin

谢谢各位大大！

yueywcy

学习了.

ll28

资源相差太多了，换芯片，或者简化设计吧。