求助：用VHDL设计串并转换模块

jazzy1230

怎样用VHDL在QuartusII中设计一个9600HZ的时钟？

另外有没有达人可以给出下列底层模块的顶层文件，也是VHDL
发送模块：
library ieee;
use ieee.std_logic_1164.all;
entity syn_s IS
port(clk:in std_logic;
Send_data:in std_logic_vector(7 downto 0);
serialut std_logic);
end syn_s;
architecture syn_s_a of syn_s is
signal Send:std_logic_vector(7 downto 0):="01111110";
begin
process(clk)
variable count:integer range 0 to 15:=0;
begin
if rising_edge(clk)then
if count=15 then serial<=Send_data(7);count:=0;
else
if(count<8)AND(count>=0)
then serial<=Send(count);
count:=count+1;
else
if(count<15)AND(count>=8)
then serial<=Send_data(count-8);count:=count+1;
else count:=0;
end if;
end if;
end if;
end if;
end process;
end syn_s_a;


波特率发生器和采样时钟：
library ieee;
use ieee.std_logic_1164.all;
entity count is
port(clk:in std_logic;clok1,clok2ut std_logic);
end count;
architecture count_a of count is
begin
process(clk)
variable count:integer range 0 to 625:=0;
begin
if rising_edge(clk)then count:=count+1;
if count=625 then clok1<='1';
count:=0;
else clok1<='0';
end if;
if(count=106 or count=313 or count=520)
then clok2<='1';
else clok2<='0';
end if;
end if;
end process;
end count_a;


接受模块：
library ieee;
use ieee.std_logic_1164.all;
entity syn_r is
port(serial,clok1,clok2:in std_logic;
P:inout std_logic_vector(7 downto 0):="11111111";
Dut std_logic_vector(0 to 7));
end syn_r;
architecture syn_r_a of syn_r is
signal C:std_logic_vector(0 to 2):="000";
signal M:std_logic;
begin
process(clok1)
variable N:integer range 0 to 7:=0;
variable flag:std_logic:='0';
constant R:std_logic_vector(7 downto 0):="11111111";
constant A:std_logic_vector(7 downto 0):="01111110";
begin
if rising_edge(clok1)then
M<=(C(0)and C(1))or(C(1)and C(2))or(C(0)and C(2));
if flag='1'then D(N)<=M;
if N=7 then N:=0;flag:='0';else N:=N+1;
end if;
else P<=M&(7 downto 1);
if(P=A)then flag:='1'<=R;
end if;
end if;
end if;
end process;
process(clok2)
variable i:integer range 0 to 2:=0;
begin
if rising_edge(clok2)then C(i)<=serial;
if i=2 then i:=0;else i:=i+1;
end if;
end if;
end process;
end syn_r_a;

dly3tf83

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mazhyn

:O
;p