状态机问题

555chip

module input_64(A,S,OD,GI,ID,GO,clk);
input clk;
input[9:0] A;
input[5:0] S;
input[7:0] OD;
input[29:0] GI;
output[7:0] ID;
output[29:0] GO;
reg[7:0] ID;
reg[29:0] GO;
wire EN;
reg[2:0] U17R;
reg[2:0] U18R;
reg[2:0] U19R;
reg[2:0] U20R;
reg[2:0] U21R;
reg[2:0] U22R;
reg[11:0] CURRENT_STATE;
reg[11:0] NEXT_STATE;

parameter //A=4'b0000,
   //B=4'b0001,
   C=4'b0010,
   D=4'b0011,
   E=4'b0100,
   F=4'b0101,
   G=4'b0110,
   H=4'b0111,
   I=4'b1000,
   J=4'b1001,
   K=4'b1010,
   L=4'b1011,
   M=4'b1100,
   N=4'b1101;
   //O=4'b1110,
   //P=4'b1111;
   
parameter U22 =12'b000000000001,
   U21 =12'b000000000010,
   U20 =12'b000000000100,
   U19 =12'b000000001000,
   U18 =12'b000000010000,
   U17 =12'b000000100000,
   U12 =12'b000001000000,
   U11 =12'b000010000000,
   U10 =12'b000100000000,
   U9 =12'b001000000000,
   U8 =12'b010000000000,
   U7 =12'b100000000000,
   //START =12'b1000000000000,
   START   =12'b000000000000;
  

assign EN=(A[9:4]==S[5:0])?1'b1:1'b0;

always @(posedge clk )
begin
if(!EN)
  begin
  CURRENT_STATE<=START;
  //CURRENT_STATE1<=START;
  end
else
  begin
  CURRENT_STATE<=NEXT_STATE;
  //CURRENT_STATE1<=NEXT_STATE1;
  end
end

always @(CURRENT_STATE or A[3:0] or EN )
begin
NEXT_STATE=12'bx;
case(CURRENT_STATE)
  START: if(A[3:0]==H) NEXT_STATE=U22;
  U22: if(A[3:0]==G) NEXT_STATE=U21;  
  U21: if(A[3:0]==F) NEXT_STATE=U20;
  U20: if(A[3:0]==E) NEXT_STATE=U19;
  U19: if(A[3:0]==D) NEXT_STATE=U18;
  U18: if(A[3:0]==C) NEXT_STATE=U17;
  U17: if(A[3:0]==I) NEXT_STATE=U12;
  U12: if(A[3:0]==J) NEXT_STATE=U11;
  U11: if(A[3:0]==K)  NEXT_STATE=U10;
  U10: if(A[3:0]==L) NEXT_STATE=U9;
  U9:  if(A[3:0]==M) NEXT_STATE=U8;
  U8:  if(A[3:0]==N) NEXT_STATE=U7;
  default:   NEXT_STATE=START;
  
endcase
end


  
  
  
always @(posedge clk )
begin
if(!EN)
  begin
  ID<=8'bz;
  GO<=30'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
  end
else
  begin
   ID<=8'bz;
   GO<=30'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
  case(NEXT_STATE)
   U22: {U22R[2:0],GO[25],GO[19],GO[13],GO[7],GO[1]}<=OD[7:0];  
   U21: {U21R[2:0],GO[26],GO[20],GO[14],GO[8],GO[2]}<=OD[7:0];
   U20: {U20R[2:0],GO[29],GO[23],GO[17],GO[11],GO[5]}<=OD[7:0];
   U19: {U19R[2:0],GO[28],GO[22],GO[16],GO[10],GO[4]}<=OD[7:0];
   U18: {U18R[2:0],GO[27],GO[21],GO[15],GO[9],GO[3]}<=OD[7:0];
   U17: {U17R[2:0],GO[24],GO[18],GO[12],GO[6],GO[0]}<=OD[7:0];
   U12: ID<={U22R[2:0],GI[25],GI[19],GI[13],GI[7],GI[1]};
   U11: ID<={U21R[2:0],GI[26],GI[20],GI[14],GI[8],GI[2]};
   U10: ID<={U20R[2:0],GI[29],GI[23],GI[17],GI[11],GI[5]};
   U9:  ID<={U19R[2:0],GI[28],GI[22],GI[16],GI[10],GI[4]};
   U8:  ID<={U18R[2:0],GI[27],GI[21],GI[15],GI[9],GI[3]};
   U7:  ID<={U17R[2:0],GI[24],GI[18],GI[12],GI[6],GI[0]};
  endcase
   
  end
end

endmodule


编译时，有这样的警告：
Warning: Design contains 4 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "A[0]"
Warning (15610): No output dependent on input pin "A[1]"
Warning (15610): No output dependent on input pin "A[2]"
Warning (15610): No output dependent on input pin "A[3]"


而且仿真时，GO输出的波形确实不以A为依据

请教各位，哪里有问题啊 ？

sixusha

NEXT_STATE=12'bx;改成NEXT_STATE=START试试

555chip

要的，我试哈