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Principles of
Verifiable RTL
Design
Second Edition
A functional coding style
supporting verification
processes in Verilog
Lionel Bening and Harry Foster
Hewlett-Packard Company
The conception of a verifiable register transfer level (RTL) phi-
osophy is a product of two factors: one, inherited seat-of-the-pants
experiences during the course of large system design; the other, the
sort of investigation which may be called “scientific.” Our philoso-
phy falls somewhere between the knowledge gained through expe-
iences and the knowledge gained through scientific research. It
corroborates on matters as to which definite knowledge has, so far,
been ascertained; but like science, it appeals to reason rather than
authority. Our philosophy consists of a fundamental set of princi-
ples, which when embraced, yield significant pay back during the
process of verification.
The need for a verifiable RTL philosophy is justified by the
complexity, density, and clock speeds of today’s chips and systems,
which continue to grow at exponential rates. This situation has
aised the cost of design errors to a critical point--where, increas-
ngly, the resources spent on the process of verification exceeds
hose spent on design. |
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发表于 2009-5-1 08:36:51
