求助：两片FPGA之间实现简单通信怎么做？

jojoguo

谢谢大家的热心回复，我正在努力 刚刚把75MHZ到100MHZ频率的转换编好，现在就准备设计一个简单的传输协议试一试

liangxia2001

具体内容具体分析

jojoguo

entity myproject is
    Port ( clk75 : in  STD_LOGIC;
           testout : out  STD_LOGIC;
           clkout : out  STD_LOGIC);
end myproject;
architecture Behavioral of myproject is
signal clk75p:std_logic;
signal z:std_logic;
signal clkfb1:std_logic;
signal clk01:std_logic;
signal clk2x1:std_logic;
signal locked1:std_logic;
signal clkdv1:std_logic;
signal clk50p:std_logic;
signal clkfb2:std_logic;
signal clk02:std_logic;
signal clk2x2:std_logic;
signal locked2:std_logic;
signal clkdv2:std_logic;
signal clk100p:std_logic;
signal clkin2:std_logic;

component CLKDLLE
-- pragma translate_off
generic (
CLKDV_DIVIDE:string:real:=1.5;
DUTY_CYCLE_CORRECTION : boolean := TRUE;
STARTUP_WAIT : string : boolean := FALSE
);
-- pragma translate_on

port (CLKIN, CLKFB : in STD_LOGIC;
      CLK0, CLK90, CLK180, CLK270, CLK2X, CLKDV, LOCKED : out std_logic);
end component;
-- Attributes
attribute CLKDV_DIVIDE : string;
attribute DUTY_CYCLE_CORRECTION : string;
attribute STARTUP_WAIT : string;
attribute CLKDV_DIVIDE of CLKU1: label is "1.5";
attribute DUTY_CYCLE_CORRECTION of CLKU1: label is "TRUE";
attribute STARTUP_WAIT of CLKU1: label is "FALSE";
attribute CLKDV_DIVIDE of CLKU2: label is "3.0";
attribute DUTY_CYCLE_CORRECTION of CLKU2: label is "TRUE";
attribute STARTUP_WAIT of CLKU2: label is "FALSE";

component IBUFG
port (I : in STD_LOGIC; O : out std_logic);
end component;
component BUFG
port (I : in STD_LOGIC; O : out std_logic);
end component;
begin
testout <= z;
clkout <= clk100p;
process(clk75p)
begin
if (clk75p 'event and clk75p='1') then
  z <= not z;
end if;
end process;

clk75ibuf: IBUFG
  port map (I => clk75,
            O => clk75p);
     
     
     
CLKU1: CLKDLLE
  port map (
       CLKIN => clk75p,
   CLKFB => clkfb1,
--   RST => reset_n,
   CLK0 => clk01,
   CLK2X => clk2x1,
   CLKDV => clkdv1,
   LOCKED=> locked1
   );
   
CLKBU1: BUFG
  port map (
   I => clkdv1,
   O => clk50p
   );
CLKBU2: BUFG
  port map (
   I => clk01,
   O => clkfb1
   );
--
--
CLKU2: CLKDLLE
  port map (
       CLKIN => clk50p,
   CLKFB => clkfb2,
--     RST => reset_n,
       CLK0 => clk02,
   CLK2X => clk2x2,
   CLKDV => clkdv2,
   LOCKED=> locked2
   );
--
CLKBU3: BUFG
  port map (
   I => clk2x2,
   O => clk100p
   );
CLKBU4: BUFG
  port map (
   I => clk02,
   O => clkfb2
   );
end Behavioral;

我编写的程序，不知道有没有太繁琐的地方，请高手帮我修改一下。还有我接下来要用100MHZ的时钟，是直接用clk100p就可以了吗？

liangkefrbu

ttl or uart or i2c 都行。。。

chutianshui

Oh, so many people from Taiwan? Why are they using complex Chinese characters?