A Systematic Approach to Solving Clock Synthesis and Clock Recovery Probledms

yxb73830

Although data rates for next generation serial busses typically double the information
capacity of the previous generation, costs are not allowed to double.  Use of low-cost
components, specifically reference clocks and integrated VCO’s, places significant
burdens on the PLL and DLL circuitry in system transmitters and receivers.  This paper
will examine how the design and performance of the various elements of a system (clocks,
PLL’s, DLL’s etc.) interact with each other and eventually contribute to the overall
system jitter budget.

Authors Biographies

James R. Stimple  

Jim Stimple is currently a Department Scientist in the Digital Signal Analysis division of
Agilent Technologies.  His engineering experience includes communication system
design as well as instrumentation for electrical spectrum analysis, optical spectrum
analysis, and high speed oscilloscopes.  He received a BSEE from Northwestern
University in 1974

Greg D. Le Cheminant  

Greg Le Cheminant is currently an applications and market development engineer for the
Digital Signal Analysis Division of Agilent Technologies located in Santa Rosa,
California.   His current work involves development of test solutions for high-speed
digital communications.  Greg holds a BSEET (1983) and MSEE (1984) from Brigham
Young University.

maylag_52

看看了！！

lixqing

Thanks.

korsh84

thanks!

zq2164

What is it about? Thanks.

maochrng

不是假的吧

plmhinc8010

Systematic Approach to Solving Clock Synthesis and Clock Recovery Probledms

JJmeow

感激不盡