急！请熟悉cadence AMS的大侠帮忙看看这个问题，先谢谢了！

hawkwgp · 发表于 2009-4-11 23:15:55

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我用Cadence的Virtuso平台的AMS混合仿真，看仿真结果发现模拟电压信号可以转换成逻辑信号，但逻辑信号不能装换成模拟电压信号(逻辑信号输出到模拟电路后输出的电压一直是0V，不会跟着逻辑的0，1变成0V，VDD）。所用的connect rule和仿真时的报告如下：
connect rule ：

// INCLUDE FILES:
`include "disciplines.vams"
`timescale 1ns / 100ps
//============================================================================
connectmodule E2L_ss (Ain, Dout);
  input Ain; electrical Ain;                   // electrical input
  output Dout; logic Dout;                      // logic output
// Supply Sensitivity attributes
  electrical (* integer supplySensitivity = "vdd_value" ; *) vdd;
  electrical (* integer groundSensitivity = "vss_value" ; *) vss;

// INSTANCE PARAMETERS:
  parameter real tr=0.2n from (0:1m);          // risetime (for defaults)
  parameter real txdel=4*tr;                   // time midrange til output X
  parameter real ttol=tr/4;                   // time tolerance of crossing
// scaled input/output levels/thresholds (0 maps to Vref, 1 maps to Vsup):
  parameter real vthi=1/1.5 from (0:1);    // frac. for high tresh (def=2/3)
  parameter real vtlo=vthi/2 from (0:vthi);  // frac. for low tresh (def=1/3)
  parameter real vtol=(vthi-vtlo)/10 from (0

vthi-vtlo)/4]; // frac. for vtol
// LOCAL VARIABLES:
  reg Dreg;             // output register
  reg Xin;                // Tx control registers
  real Kin;             // input relative to supply range
  real txdig;             // tx in timescale units
  real vtlox,vthix;       // thresholds for transition to X state

//============================================================================
  initial begin
txdig=txdel/1n;       // digital delay midlevel to X  (ASSUMES TIMESCALE)
Dreg=(Kin>vthi)? 1'b1 : (Kin<vtlo)? 1'b0 : 1'bx;  // initial level
Xin=0;                // initially not in X delay region.
vtlox=vtlo+2*vtol;    // lo-to-x threshold point
vthix=vthi-2*vtol;    // hi-to-x threshold point
  end
// Relative input level (maps input to range of 0=vref, 1=vsup):
  analog  Kin = V(Ain,vss)/max(V(vdd,vss),1m);

// Convert analog signal to high/low and X/notX:
  always @(above(Kin-vthi,ttol,vtol))
   begin Dreg=1; Xin=0; end                // analog XtoH
  always @(above(vtlo-Kin,ttol,vtol))
   begin Dreg=0; Xin=0; end                // analog XtoL
  always @(above(vthix-Kin,ttol,vtol))
   if (Kin<vthi && Dreg!==1'bx) Xin=1;       // analog HtoX
  always @(above(Kin-vtlox,ttol,vtol))
   if (Kin>vtlo && Dreg!==1'bx) Xin=1;       // analog LtoX
// Wait for txdel before driving output to X:
  always @(posedge(Xin)) begin :GoToX          // input changed to X
#(txdig)                                  // wait for X time delay
if (Kin>vtlo && Kin<vthi) Dreg=1'bx;       // goto X if still between
else Xin=0;                               // else clear the X flag
  end
  always @(negedge(Xin)) disable GoToX;       // cancel out-to-X on Xin=0
  assign  Dout=Dreg;                            // assign register to output
endmodule

// INCLUDE FILES:
`include "disciplines.vams"
`timescale 1ns / 100ps
//============================================================================
connectmodule L2E_ss(Din,Aout);
input Din; logic Din;       // digital input signal
output Aout; electrical Aout;  // analog output signal

// Supply Sensitivity attributes
electrical (* integer supplySensitivity = "vdd_value" ; *) vdd;
electrical (* integer groundSensitivity = "vss_value" ; *) vss;

// INSTANCE PARAMETERS:
parameter real tr=0.2n;       // risetime of analog output
parameter real rout=200;    // output resistance
// scaled output levels (0 maps to Vref, 1 maps to Vsup):
parameter real vlo=0 from [0:1);             // frac. output low level
parameter real vhi=1 from (vlo:1];          // frac. output high level
parameter real vxz=(vhi+vlo)/2 from [vlo:vhi]; // frac for XZ state voltage
// LOCAL VARIABLES:
reg Dreg;                   // output is a register
real Kout,Kres;             // relative output voltage & resistance states
real Vout,Rval;             // output V & R with transitions

//============================================================================
initial begin
Dreg = Din;                // initial logic writeback
Kout = (Din===1'b0)? vlo : (Din===1'b1)? vhi : vxz; // initial V
Kres = (Din===1'bz)? 1 : 0;                         // initial R
end
always @Din begin
Dreg = Din;                // logic writeback follows level.
case(Din)
   1'b0:  begin  Kout=vlo; Kres=0; end  // low state
   1'b1:  begin  Kout=vhi; Kres=0; end  // high state
   1'bx:  begin  Kout=vxz; Kres=-0.1; end  // X (impedance is 0.2*rout)
   1'bz:  begin  Kout=vxz; Kres=1; end  // Z (impedance is 80K*rout)
endcase
end
analog begin
Vout = V(vdd,vss)*transition(Kout,0,tr,tr); // add risetimes & supply dep
Rval = rout*(1+80K*pow(transition(Kres,0,tr,tr),5)); // resistor with rise
I(Aout) <+ (V(Aout,vss)-Vout)/Rval;             // drive output
end
assign Din = Dreg;          // assign digital value to input pin.
endmodule

// 'ConnRules_ss.vams' - Verilog-AMS supply sensitive connection rules file.
// last revised: 1/30/04 (ronv)
// This file is a template for definition of rules for a particular
// logic family.  Values for some typical parameters are defined here,
// then used in the three sets of connections rules below.
// See the "README.txt" file for a more complete usage description.
`define VHI  2
`define VLO  0
`define Vthi  0.67
`define Vtlo  0.33
`define Tr 0.4n
`define Rlo 200
`define Rhi 200
`define Rx 40
`define Rz 10M
connectrules ConnRules_ss_mid;
  connect E2L_ss #( .vthi(`Vthi), .vtlo(`Vtlo), .tr(`Tr) );
  connect L2E_ss #( .tr(`Tr), .rout(`Rlo) );
  connect Bidir_ss #( .vthi(`Vthi), .vtlo(`Vtlo),
   .tr(`Tr), .tf(`Tr), .tx(`Tr), .tz(`Tr),
   .rlo(`Rlo), .rhi(`Rhi), .rx(`Rx), .rz(`Rz) );
endconnectrules

LOG print:

Warning from spectre.
`gpdk090_resm1': `tr' is not a valid parameter for `resistor' models.
`gpdk090_resm1': `level' is not a valid parameter for `resistor' models.
`gpdk090_resm1': `dta' is not a valid parameter for `resistor' models.
`gpdk090_resm2': `tr' is not a valid parameter for `resistor' models.
`gpdk090_resm2': `level' is not a valid parameter for `resistor' models.
      Further occurrences of this warning will be suppressed.
ncelab: *W,DEFSENS: Supply and ground sensitivities are ignored in default discipline resultion mode.
Connecting to License Server ... Done.
*****************************************************************************
*
*  ultrasim version 6.1.0.283 32bit 02/07/2007 22:33 (amsfarmlnx20)
*  Virtuoso (R) Ultrasim Full-chip Simulator
*  Copyright(C) 2001-2004, Cadence Design Systems, Inc.
*  USER: eda HOST: rhel4 HOSTID: 7F0100 PID: 10429
*  Memory: available: 65.2369 MB  physical: 1.0604 GB
*  CPU(1 of 1): CPU0 Intel(R) Pentium(R) Dual  CPU  T2310  @ 1.46GHz 1463.326MHz
*
*  Starting time: Sat Apr 11 22:39:34 2009
*
*****************************************************************************
Successful checkout of ULTRASIM license with total wait time of 0 sec.
Loading /CDS/cadence/IUS57/tools.lnx86/cmi/lib/5.0/libinfineon_sh.so ...
Loading /CDS/cadence/IUS57/tools.lnx86/cmi/lib/5.0/libnortel_sh.so ...
Loading /CDS/cadence/IUS57/tools.lnx86/cmi/lib/5.0/libphilips_sh.so ...
Loading /CDS/cadence/IUS57/tools.lnx86/cmi/lib/5.0/libsparam_sh.so ...
Loading /CDS/cadence/IUS57/tools.lnx86/cmi/lib/5.0/libstmodels_sh.so ...
File read: /home/eda/AMS/models/spectre/gpdk090.scs
File read: /home/eda/AMS/models/spectre/gpdk090_mos.scs
File read: /home/eda/AMS/models/spectre/gpdk090_mos.scs
File read: /home/eda/AMS/models/spectre/gpdk090_mos.scs
File read: /home/eda/AMS/models/spectre/gpdk090_mos.scs
File read: /home/eda/AMS/models/spectre/gpdk090_mos.scs
File read: /home/eda/AMS/models/spectre/gpdk090_mos.scs
File read: /home/eda/AMS/models/spectre/gpdk090_mos_iso.scs
File read: /home/eda/AMS/models/spectre/gpdk090_moscap.scs
File read: /home/eda/AMS/models/spectre/gpdk090_moscap.scs
File read: /home/eda/AMS/models/spectre/gpdk090_moscap.scs
File read: /home/eda/AMS/models/spectre/gpdk090_moscap.scs
File read: /home/eda/AMS/models/spectre/gpdk090_moscap.scs
File read: /home/eda/AMS/models/spectre/gpdk090_moscap.scs
File read: /home/eda/AMS/models/spectre/gpdk090_resistor.scs
File read: /home/eda/AMS/models/spectre/gpdk090_resistor.scs
File read: /home/eda/AMS/models/spectre/resd_va.va
File read: /home/eda/AMS/models/spectre/gpdk090_resistor.scs
File read: /home/eda/AMS/models/spectre/gpdk090_capacitor.scs
File read: /home/eda/AMS/models/spectre/gpdk090_diode.scs
File read: /home/eda/AMS/models/spectre/gpdk090_diode.scs
File read: /home/eda/AMS/models/spectre/gpdk090_diode.scs
File read: /home/eda/AMS/models/spectre/gpdk090_diode.scs
File read: /home/eda/AMS/models/spectre/gpdk090_diode.scs
File read: /home/eda/AMS/models/spectre/gpdk090_bipolar.scs
Parser: user time: 0:00:00 (0.340 sec), system time: 0:00:00 (0.170 sec), real time: 0:00:00 (0.620 sec)
Parser: memory:                      1.3104 MB total:       8.6488 MB
File read: /home/eda/simulation/sim/ams/config/netlist/amsControl.scs
****WARNING:UFE-5153****: The option parameter: `reltol` is not supported in `options` statement (ignored).

****WARNING:UFE-5153****: The option parameter: `vabstol` is not supported in `options` statement (ignored).

****WARNING:UFE-5153****: The option parameter: `iabstol` is not supported in `options` statement (ignored).

****WARNING:UFE-5153****: The option parameter: `rforce` is not supported in `options` statement (ignored).

****WARNING:UFE-5153****: The option parameter: `maxnotes` is not supported in `options` statement (ignored).

###The following type of message is not going to be printed any more.###
****WARNING:UFE-5153****: The option parameter: `digits` is not supported in `options` statement (ignored).

(Use .usim_opt warning_limit=value to set the limit.)

****WARNING:UFE-4015****: Argument not supported, save=none (ignored).
FILE:/home/eda/simulation/sim/ams/config/netlist/amsControl.scs, LINE#:49
tran tran stop=1000u save=none write="spectre.ic" writefinal="spectre.fc"

****WARNING:UFE-4015****: Argument not supported, maxiters=5 (ignored).
FILE:/home/eda/simulation/sim/ams/config/netlist/amsControl.scs, LINE#:54
+ maxiters=5 annotate=status

****WARNING:UFE-4015****: Argument not supported, annotate=status (ignored).
FILE:/home/eda/simulation/sim/ams/config/netlist/amsControl.scs, LINE#:54
+ maxiters=5 annotate=status
Parser: user time: 0:00:00 (0.010 sec), system time: 0:00:00 (0.010 sec), real time: 0:00:00 (0.010 sec)
Parser: memory:                      0 B total:       8.7799 MB
User Option Summary:
.usim_opt del_allnode_inst=no
.usim_opt wf_output_format=verilog
.usim_opt output_upper=0 ade=1 wf_spectre_syntax=1
Total Options statements: 3
-------------------------------------
Relinquished control to SimVision...
ncsim>
ncsim> source /CDS/cadence/IUS57/tools/inca/files/ncsimrc
ncsim>
ncsim> # This is the NC-SIM(R) probe command file
ncsim> # used in the AMS-ADE integration.
ncsim>
ncsim>
ncsim> #
ncsim> # Database settings
ncsim> #
ncsim> if { [info exists ::env(AMS_RESULTS_DIR) ] } { set AMS_RESULTS_DIR $env(AMS_RESULTS_DIR)} else {set AMS_RESULTS_DIR "/home/eda/simulation/sim/ams/config/psf"}
/home/eda/simulation/sim/ams/config/psf
ncsim> database -open ams_database -into $AMS_RESULTS_DIR -default
Created default SHM database ams_database
ncsim>
ncsim> #
ncsim> # Probe settings
ncsim> #
ncsim>

hawkwgp · 发表于 2009-4-12 21:00:26

难道这里没有人用cadence的verilog AMS做混合信号仿真么？请大侠们不吝赐教啊！

blue1101 · 发表于 2009-5-3 19:01:20

装MMSIM后是否还需要装ius才能做混合仿真?没有用过MMSIM,不懂

haoshs · 发表于 2009-6-2 08:42:56

LZ,能给个license吗？
我的license不能做AMS仿真，等我装好license可以交流一下！

st_james · 发表于 2009-6-3 16:58:20

no idea

pkmanabc · 发表于 2009-8-16 22:26:12

hope can help

forrest320 · 发表于 2009-9-15 20:03:55

学习学习。。。。。。。。

dongdong2 · 发表于 2009-9-22 20:53:03

请问:verilog-AMS写的程序能仿真S参数么?

malesky · 发表于 2009-12-1 20:20:16

6# pkmanabc

richardxie · 发表于 2009-12-2 12:25:57

4# haoshs
对，共享一下License，共同学习
我正在准备



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急！请熟悉cadence AMS的大侠帮忙看看这个问题，先谢谢了！

马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。

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