最新出炉的2009年4月 JSSC

jeff_zx

1、A Low Power 6-bit Flash ADC With Reference Voltage and Common-Mode Calibration
2、1.2-V 250-mW 14-b 100-MS/s Digitally Calibrated Pipeline ADC in 90-nm CMOS
3、A 9.4-bit, 50-MS/s, 1.44-mW Pipelined ADC Using Dynamic Source Follower Residue Amplification
4、A 1-V 450-nW Fully Integrated Programmable Biomedical Sensor Interface Chip
5、A 0.7-V 870-$mu$ W Digital-Audio CMOS Sigma-Delta Modulator
6、A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping
7、Single-Inductor Multi-Output (SIMO) DC-DC Converters With High Light-Load Efficiency and Minimized Cross-Regulation for Portable Devices
8、Regulated Switched-Capacitor Doubler With Interleaving Control for Continuous Output Regulation
9、Next Generation Intelˉ Core? Micro-Architecture (Nehalem) Clocking
10、A 167-Processor Computational Platform in 65 nm CMOS
11、A Low-Voltage Processor for Sensing Applications With Picowatt Standby Mode
12、Alignment-Independent Chip-to-Chip Communication for Sensor Applications Using Passive Capacitive Signaling
13、An Asynchronous Power Aware and Adaptive NoC Based Circuit
14、A Sub-$mu$ s Wake-Up Time Power Gating Technique With Bypass Power Line for Rush Current Support
15、A 256 mW 40 Mbps Full-HD H.264 High-Profile Codec Featuring a Dual-Macroblock Pipeline Architecture in 65 nm CMOS
16、A 0.7 V Single-Supply SRAM With 0.495 $mu$m$^{2}$ Cell in 65 nm Technology Utilizing Self-Write-Back Sense Amplifier and Cascaded Bit Line Scheme
17、Process, Temperature, and Supply-Noise Tolerant 45$~$nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits
18、A 0.6 V Dual-Rail Compiler SRAM Design on 45 nm CMOS Technology With Adaptive SRAM Power for Lower VDD_min VLSIs
19、A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS
20、Novel Co-Design of NAND Flash Memory and NAND Flash Controller Circuits for Sub-30 nm Low-Power High-Speed Solid-State Drives (SSD)
21、A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface
22、A 350 $mu$ W CMOS MSK Transmitter and 400 $mu$W OOK Super-Regenerative Receiver for Medical Implant Communications
23、All-Digital Outphasing Modulator for a Software-Defined Transmitter
24、A Wideband Supply Modulator for 20 MHz RF Bandwidth Polar PAs in 65 nm CMOS
25、A 1 Gb/s Mixed-Signal Baseband Analog Front-End for a 60 GHz Wireless Receiver
26、A 70 dB MTPR Integrated Programmable Gain/Bandwidth Fourth-Order Chebyshev High-Pass Filter for ADSL/VDSL Receivers in 65 nm CMOS
27、A 12-Gb/s 11-mW Half-Rate Sampled 5-Tap Decision Feedback Equalizer With Current-Integrating Summers in 45-nm SOI CMOS Technology
28、A Multi-Standard 1.5 to 10 Gb/s Latch-Based 3-Tap DFE Receiver With a SSC Tolerant CDR for Serial Backplane Communication

jcchan

感謝大大無私的分享,感恩啦!!!

jeff_zx

:handshake :handshake :handshake

pppwww

thanks for sharing

lcl6000

無私的分享

jeff_zx

Jason_ke

很好很强大，3x

BB600

Very instant informations

f88chengling

很不错的东西啊

jeff_zx

:victory: :victory: