【SI新书】Timing Analysis and Simulation for Signal Integrity Engineers

baoer1_1

回复 1# cheng520so


    谢谢楼主分享

iamking2013

非常感谢。

hhjankin

great book!

pig_lee

好东西，必须顶啊。。。。。。

mimiman

very goooooood

ee511

Thanks so much for sharing the book

ee511

Timing Analysis and Simulation for Signal Integrity Engineers

daisyboy

zhemeda

daisyboy

比较费钱

sathya

Design Compiler Compatibility
The PrimeTime static timing analysis tool is designed to work well with the most commonly used synthesis tool, Design Compiler. PrimeTime and Design Compiler are compatible in the following ways:
•Both tools use the same technology libraries and read the same design data files in .db and .ddc formats.
•Both tools share many of the same commands, such as the create_clock, set_input_delay, and report_timing commands. Shared commands are identical or very similar in operation.
•Both tools share the same delay calculation algorithms and generally produce identical delay results.
•Timing reports generated by both tools are very similar.
•PrimeTime can capture the timing environment of a synthesizable subcircuit and write this timing environment as a series of Design Compiler commands. You can use the resulting script in Design Compiler to define the timing constraints for synthesis or logic optimization of the subcircuit.
•Both tools support the Synopsys Design Constraints (SDC) format for specifying design intent, including the timing and area constraints for a design.
Although Design Compiler has its own built-in static timing analysis capability, PrimeTime has better speed, capacity, and flexibility for static timing analysis, and offers many features not supported