Advanced Xilinx Fpga Design With Ise 指南

scsunjia

贴个目录
Section 1 : Optimize Your Design for Xilinx Architecture
– Core Generator System
• Lab : Core Generator System Flow
Section 2 : Achieving Timing Closure
– Timing Closure with Timing Analyzer
– Global Timing Constraints
• Lab : Global Timing Constraints
– Advance Timing Constraints
• Lab : Achieving Timing Closure with Advance Constraints
Section 3 : Improve Your Timing
– Floorplanner
• Lab: Floorplanner
Section 4 : Reduce Implementaion Time
– Incremental Design Techniques
• Lab : IDT Flow
– Modular Design Techniques
• Lab : MDT Flow
Section 5 : Reduce Debug Time
– FPGA Editor: Viewing and Editing a Routed Design
• Lab: FPGA Editor
Section 6 : On-Chip Verification and Debugging
– ChipScope Pro
• Demo
Section 7 : Course Summary
Optional Topics
– Power Estimation with Xpower
– Advance Implementation Options
– Embedded Solutions with Power PC/MicroBlaze and Embedded Development Kit (EDK)
– Xtreme DSP Solutions with System Generator

要是能把lab的代码页发上来就更好了。

xinqrs

谢谢分享啊！楼主好人哦！

crimson

正想看看ISE的书，本人有点郁闷近来

William_smt

好好好，下来看看

pansouthline

eetop

flyingtiger

谢谢，看看

BIGHAMMER

好东西，谢谢

unclebearbear

Thanks a lot

baiyingli17

资料太老了

zhyoisa

资料不错，多谢