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发表于 2009-9-13 02:39:05
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原帖由 waley 于 2009-9-13 00:41 发表 那對於 SSC 又要如何考慮? SDM's OSR/Order/ PLL's bandwidth 要如何決定 ?
For SSC case, However it is a little bit different. The thing is depending on what the profile of SS is. In general, SS frequency must be low enough so that its shape is NOT corrupted by the loop. In case the SS frequency is comparable to PLL BW, there is a must to do something like pre-shaping before entering SDM loop so that the final SS shape still looks ok |
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