Basically, SDM has a high pass noise shaping in many case of the FNPLL design. You can design a SDM with effective bandwidth lower than the PLL loop bandwidth so that the SDM noise will be removed by ...
For SSC case, However it is a little bit different. The thing is depending on what the profile of SS is. In general, SS frequency must be low enough so that its shape is NOT corrupted by the loop. In case the SS frequency is comparable to PLL BW, there is a must to do something like pre-shaping before entering SDM loop so that the final SS shape still looks ok