Synopsys Power Compiler实验

jkkl1983 · 发表于 2009-5-15 16:39:13

Synopsys Power Compiler实验

jkkl1983 · 发表于 2009-5-15 16:41:04

Synopsys Power Compiler实验

jkkl1983 · 发表于 2009-5-15 16:51:10

Synopsys Power Compiler实验

xzar · 发表于 2009-5-21 21:00:46

good!good good

xzar · 发表于 2009-5-21 21:01:48

thank you very much

xzar · 发表于 2009-5-21 21:03:43

thank you very much

xzar · 发表于 2009-5-21 21:05:23

actually, power compiler extract clock gating on your design for power saving. while only prime power does the power analysis.

the general flow is as follows:
1. read_verilog
2. read_spef (if available)
3. read_vcd
4. calculate_power
5. report_power
you can get the detail usage in Prime Power. have fun...

CNC · 发表于 2009-5-21 21:20:46

up!!!!!!!!!!!!!!!!!!!!!!!!

CNC · 发表于 2009-5-21 21:22:02

up!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

CNC · 发表于 2009-5-21 21:23:14

up!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

Synopsys Power Compiler实验

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