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[原创] 使用FPGA设计DSP的新流程

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发表于 2006-1-20 02:33:35 | 显示全部楼层 |阅读模式

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本帖最后由 cjsb37 于 2013-4-29 09:16 编辑

目前诸如DSP Builder等新的设计工具为DSP工程师提供了设计DSP的崭新的思路,该文介绍了一种基于传统软件设计方式,使用FPGA设计DSP的流程。

Traditionally, DSP designers had to implement their systems in FPGAs using the hardware flow based on a HDL language such as Verilog HDL and VHDL. New DSP tools such as DSP Builder, SOPC Builder, and a complete software development platform now enable DSP designers to follow a software-based design flow while targeting FPGAs as shown in Figure 2.
Altera FPGAs with embedded processors support a software-based design flow. Altera provides software development tools including the GNU Pro toolset for compiling, debugging, assembling and linking software designs. These software designs can then be downloaded to an FPGA using either on-chip RAM or an external memory device.
Software Combined with Hardware Acceleration
Embedded processors and hardware acceleration offer the flexibility, performance, and cost effectiveness in a development flow that is familiar to software developers. A DSP designer can combine a software design flow along with hardware acceleration. For example, the developer can use Altera's DSP IP or develop their own custom instruction to accelerate those tasks in the FPGA. The system control code along with the other low-performance DSP algorithms can be run on a Nios embedded processor.
Altera also provides system-level tools such as SoPC Builder for system-level partitioning and integration. Designers can use SOPC Builder to build entire hardware systems by combining the embedded processor, such as a Nios embedded processor, system peripherals, as well as IP MegaCore functions.
Altera's DSP Builder tool provides an interface from Simulink directly to the FPGA hardware. The DSP Builder tool simplifies hardware implementation of DSP functions, provides a system-level verification tool to the system engineer who is not necessarily familiar with HDL design flow, and allows the system engineer to implement DSP functions in FPGAs without learning HDL. Additionally, designers can incorporate the designs created by DSP Builder into a SOPC Builder system for a complete DSP system implementation.






发表于 2006-9-6 21:11:08 | 显示全部楼层
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