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1.A 64 mW High Picture Quality H.264/MPEG-4 Video Codec IP for HD Mobile Applications in 90 nm CMOS
2.A 2 Gb/s Bi-Directional Inter-Chip Data Transceiver With Differential Inductors for High Density Inductive Channel Array
3.A 195 mW, 9.1 MVertices/s Fully Programmable 3-D Graphics Processor for Low-Power Mobile Devices
4.A 512 Mb Two-Channel Mobile DRAM (OneDRAM) With Shared Memory Array
5.Backgate Bias Accelerator for sub-100 ns Sleep-to-Active Modes Transition Time
6.A 130 nm CMOS 6-bit Full Nyquist 3 GS/s DAC
7.A Linearization Technique for RF Receiver Front-End Using Second-Order-Intermodulation Injection
8.An Infinite Phase Shift Delay-Locked Loop With Voltage-Controlled Sawtooth Delay Line
9.Low-Area Active-Feedback Low-Noise Amplifier Design in Scaled Digital CMOS
10.Digital Adaptive IIP2 Calibration Scheme for CMOS Downconversion Mixers
11.A Variable-Phase Ring Oscillator and PLL Architecture for Integrated Phased Array Transceivers
12.A 14 mW Fractional-N PLL Modulator With a Digital Phase Detector and Frequency Switching Scheme
13.A Continuous-Time ADC/DSP/DAC System With No Clock and With Activity-Dependent Power Dissipation
14.A CMOS 1 Gb/s 5-Tap Fractionally-Spaced Equalizer
15.A 40 Gb/s CMOS Serial-Link Receiver With Adaptive Equalization and Clock/Data Recovery
16.A 430 MHz, 280 mW Processor for the Conversion of Cartesian to Polar Coordinates in 0.25 $muhbox{m}$ CMOS
17.Techniques to Extend Canary-Based Standby $V_{DD}$ Scaling for SRAMs to 45 nm and Beyond
18.Low-Power Dynamic Memory Word Line Decoding for Static Random Access Memories
19.Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test
20.A Single-Photon Avalanche Diode Array for Fluorescence Lifetime Imaging Microscopy
21.A CMOS Fingerprint System-on-a-Chip With Adaptable Pixel Networks and Column-Parallel Processors for Image Enhancement and Recognition |
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