Synchronization_and_Arbitration_in_Digital_Systems__netbks.com

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Preface
Most books on digital design only briefl y touch on the design of
synchronizers and arbiters, with maybe two or three pages in a 300
page book, or a chapter at most. This is because there was no real need
for it in the early years of computer design. Processors were largely selfcontained
and used a single clock, so interfacing the processor to slow
peripherals, or other processors was not seen as a major task. The fact
that it is not simple emerged in the 1970s and 1980s when data rates
between processors increased, and sometimes systems with more than
one time zone were being designed. Despite frequent synchronization
failures because of lack of understanding of the design principles at
that time, synchronization still did not make it into the standard literature,
and very little has been written since about how they should be
designed. More recently processors are being designed with many more
high-speed ports linked to networks, and the systems themselves are
often made up of several core processors connected to an internal bus
or network on chip. This means that processors operating on different
time frames must communicate at high data rates, and when two or
more processors request access to a common resource, there has to be
some arbitration to decide which request to deal with fi rst.
The need for synchronizers to ensure that data coming from one time
frame is readable in another, and arbiters to ensure that a clean decision
is taken has always been there, but the understanding has not. Our
aim is to promote good design in these areas because the number of
timing interface circuits is escalating as the number of multiprocessor
systems grows. A single processor interfacing to the real world through
a few slow peripherals will not have many problems, but as the number
of input/output ports increases, and the data rates increase, diffi culties
with reliability, data latency and design robustness will also increase.

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