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发表于 2011-10-19 22:00:48
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//---------------------------------------------------//
module mux32N(sel,data_in0,data_in1,data_out);
input sel;
input [31:0] data_in0;
input [31:0] data_in1;
output [31:0] data_out;
assign data_out = sel ? ~data_in1 : ~data_in0;
endmodule
module mux32(sel,data_in0,data_in1,data_out);
input sel;
input [31:0] data_in0;
input [31:0] data_in1;
output [31:0] data_out;
assign data_out = sel ? data_in1 : data_in0;
endmodule
module RR(sel,data_in,data_out);
input [4:0] sel;
input [31:0] data_in;
output [31:0] data_out;
wire [31:0] P4,P3,P2,P1,P0;
mux32N U4(.sel ( sel[4] ),
.data_in0( data_in ),
.data_in1( {data_in[15:0],data_in[31:16]} ),
.data_out( P4 )
);
mux32N U3(.sel ( sel[3] ),
.data_in0( P4[31:0] ),
.data_in1( {P4[7:0],P4[31:8]} ),
.data_out( P3 )
);
mux32N U2(.sel ( sel[2] ),
.data_in0( P3[31:0] ),
.data_in1( {P3[3:0],P3[31:4]} ),
.data_out( P2 )
);
mux32N U1(.sel ( sel[1] ),
.data_in0( P2[31:0] ),
.data_in1( {P2[1:0],P2[31:2]} ),
.data_out( P1 )
);
mux32 U0(.sel ( sel[0] ),
.data_in0( P1[31:0] ),
.data_in1( {P1[0],P1[31:1]} ),
.data_out( data_out )
);
endmodule |
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