（经典资料）Principles of Verifiable RTL Design.2nd.Edition

nightyboy

Principles of Verifiable RTL Design.2nd.Edition

The first edition of Principles of Verifiable RTL Design offered
a common sense method for simplifying and unifying assertion
specification. This method includes creating a set of predefined
specification modules that can be instantiated within the designer’s
RTL.
Since the release of the first edition, an industry wide initiative
for assertion specification has emerged based on ideas presented in
our book. This initiative, known as Open Verification Library Initiative
(www.verificationlib.org), provides an assertion interface standard
that allows the design engineer to capture many interesting
properties of the design and precludes the need to introduce new
HDL constructs (i.e., extensions to Verilog are not required). Furthermore,
this standard enables the design engineer to “specify
once,” then target the same RTL assertion specification over multiple
verification processes, such as traditional simulation, semi-formal
and formal verification tools. We view the Open Verification
Library Initiative as an empowering technology that will benefit
design and verification engineers, and establish unity among the
EDA community (i.e., providers of testbench generation tools, traditional
simulators, commercial assertion checking support tools,
symbolic simulation, and semi-formal and formal verification
tools). We are delighted that our book has provided a positive influenced
on both design teams and the EDA industry.
This second edition of Principles of Verification RTL Design
expands the discussion of assertion specification by including a new
chapter, titled Coverage, Events and Assertions. All assertions
exampled are aligned with the Open Verification Library Initiative
proposed standard. In addition, the second edition provides
expanded discussions on the following topics:
start-up verification
the place for 4-state simulation
race conditions
RTL-style - synthesizable RTL. (unambiguous mapping to
gates)
more “bad stuff”
Reorganized
topic
presentation.
21 principles
combined into
18.
Since the first edition, we have presented tutorials on Verifiable
RTL Design in dozens of venues to a total of over 2,000 design
engineers. Based on their feedback, we have tuned up the order of
presentation in many chapters, but particularly in Chapter 4.
Of the 21 principles from the first edition, 15 remain intact. The
changes in principles in the second edition include:
Two principles
change their
wording.
Superlog and
SystemC.
folding the Test Expression Observability Principle into the
Cutpoint Identification Principle,
combining the Indentation Principle, the Code Inclusion
Control Principle, and the Entry Point Naming Principle into
a single Consistency Principle, and
changing the Meta-comment Principle into the Property
Principle, and the Object-Oriented Hardware Design Principle
into the Object-Based Hardware Design Principle.
Keeping
verification
current.
Visit our web
site.
At the time of this writing, verification processes and tools for
Superlog and SystemC are not ready. Without design project experience,
RTL verification based on these languages could only be
projections.
Our goal in releasing a second edition is to keep the topic current.
The bibliography has been expanded to include the latest
research. Every chapter of the book has been enhanced based on
positive and critical feedback. Finally, the overall book’s look and
feel has been enhanced to a more contemporary appearance.

nightyboy

support by myself

jungswee

i support you ,too

jungswee

but i dont have enough money

minidust

see a see!

zavi

thanks for sharing

jesse1013000

Thanks a lot。

xlove

xie xie...........

xlove

xie xie.............

xlove

xie xie.........