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CMOS Analog Circuit Design Page 6.0-1
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
CHAPTER 6 - CMOS OPERATIONAL AMPLIFIERS
Chapter Outline
6.1 Design of CMOS Op Amps
6.2 Compensation of Op Amps
6.3 Two-Stage Operational Amplifier Design
6.4 Power Supply Rejection Ratio of the Two-Stage Op Amp
6.5 Cascode Op Amps
6.6 Simulation and Measurement of Op Amps
6.7 Macromodels for Op Amps
6.8 Summary
Goal
Understand the analysis, design, and measurement of simple CMOS op amps
Design Hierarchy
Blocks or circuits
(Combination of primitives, independent)
Sub-blocks or subcircuits
(A primitive, not independent)
Functional blocks or circuits
(Perform a complex function)
Fig. 6.0-1
Chapter 6
The op amps of this chapter are unbuffered and are OTAs but we will use the generic term “op amp”.
CMOS Analog Circuit Design Page 6.1-1
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
SECTION 6.1 - DESIGN OF CMOS OPERATIONAL AMPLIFIERS
High-Level Viewpoint of an Op Amp
Block diagram of a general, two-stage op amp:
Differential
Transconductance
Stage
High
Gain
Stage
Output
Buffer
Compensation
Circuitry
Bias
Circuitry
+
-
v1 vOUT
v2
vOUT'
Fig. 6.1-1
• Differential transconductance stage:
Forms the input and sometimes provides the differential-to-single ended conversion.
• High gain stage:
Provides the voltage gain required by the op amp together with the input stage.
• Output buffer:
Used if the op amp must drive a low resistance.
• Compensation:
Necessary to keep the op amp stable when resistive negative feedback is applied.
CMOS Analog Circuit Design Page 6.1-2
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Ideal Op Amp
Symbol:
+
-
+
-
+
-
v1
v2
vOUT = Av(v1-v2)
VDD
VSS
Fig. 6.1-2
+
-
i1
i2
+
-
vi
Null port:
If the differential gain of the op amp is large enough then input terminal pair becomes a null port.
A null port is a pair of terminals where the voltage is zero and the current is zero.
I.e.,
v1 - v2 = vi = 0
and
i1 = 0 and i2 = 0
Therefore, ideal op amps can be analyzed by assuming the differential input voltage is zero and that no current
flows into or out of the differential inputs.
CMOS Analog Circuit Design Page 6.1-3
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
General Configuration of the Op Amp as a Voltage Amplifier
+
- +
-
+
-
+
-
v1
v2 vout
Fig. 6.1-3
vinp
vinn
R1 R2
Noninverting voltage amplifier:
vinn = 0 ⇒ vout =

 
  R1+R2
R1
vinp
Inverting voltage amplifier:
vinp = 0 ⇒ vout = -

 
  
R2
R1
vinn
CMOS Analog Circuit Design Page 6.1-4
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Example 6.1-1 - Simplified Analysis of an Op Amp Circuit
The circuit shown below is an inverting voltage amplifier using an op amp. Find the voltage transfer
function, vout/vin.
+
- +
-
+
-
+
-
vin vi vout
R1 R2
ii
i1 i2
Virtual Ground Fig. 6.1-4
Solution
If the differential voltage gain, Av, is large enough, then the negative feedback path through R2 will
cause the voltage vi and the current ii shown on Fig. 6.1-4 to both be zero. Note that the null port becomes
the familiar virtual ground if one of the op amp input terminals is on ground. If this is the case, then we can
write that
i1 =
vin
R1
and
i2 =
vout
R2
Since, ii = 0, then i1 + i2 = 0 giving the desired result as
vout
vin
= -
R2
R1
.
CMOS Analog Circuit Design Page 6.1-5
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Linear and Static Characterization of the Op Amp
A model for a nonideal op amp that includes some of the linear, static nonidealities:
+
-
v2
v1
v1
CMRR
VOS
Ricm
Ricm
in2
en2
IB1
IB2
Cid Rid
Rout vout
Ideal Op Amp
Fig. 6.1-5
*
where
Rid = differential input resistance
Cid = differential input capacitance
Ricm = common mode input resistance
VOS = input-offset voltage
IB1 and IB2 = differential input-bias currents
IOS = input-offset current (IOS = IB1-IB2)
CMRR = common-mode rejection ratio
e
2n
= voltage-noise spectral density (mean-square volts/Hertz)
i
2n
= current-noise spectral density (mean-square amps/Hertz)
CMOS Analog Circuit Design Page 6.1-6
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Linear and Dynamic Characteristics of the Op Amp
Differential and common-mode frequency response:
Vout(s) = Av(s)[V1(s) - V2(s)] ± Ac(s) 
 
  
V1(s)+V2(s)
2
Differential-frequency response:
Av(s) =
Av0
  
  
s
p1
- 1
  
  
s
p2
- 1
  
  
s
p3
- 1 ···
where p1, p2, p3,··· are the poles of the differential-frequency response.
0dB
20log10(Av0)
|Av(jω)| dB
Asymptotic
Magnitude
Actual
Magnitude
ω1
ω2 ω3 ω
-6dB/oct.
-12dB/oct.
-18dB/oct.
GB
Fig. 6.1-6
CMOS Analog Circuit Design Page 6.1-7
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Other Characteristics of the Op Amp
Power supply rejection ratio (PSRR):
PSRR =
ΔVDD
ΔVOUT
Av(s) =
Vo/Vin (Vdd = 0)
Vo/Vdd (Vin = 0)
Input common mode range (ICMR):
ICMR = the voltage range over which the input common-mode signal can vary without
influence the differential performance
Slew rate (SR):
SR = output voltage rate limit of the op amp
Settling time (Ts):
Ts = time needed for the output of the op amp to reach a final value to with a predetermined
tolerance when excited by a small signal. (SR is large signal excitation)
+
-
Settling Time
Final Value
Final Value + ε
Final Value - ε
ε
ε
vOUT(t)
0 t
0
vOUT
vIN
Ts Fig. 6.1-7
Upper Tolerance
Lower Tolerance
CMOS Analog Circuit Design Page 6.1-8
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Classification of CMOS Op Amps
Categorization of op amps:
Conversion
Classic Differential
Amplifier
Modified Differential
Amplifier
Differential-to-single ended
Load (Current Mirror)
Source/Sink
Current Loads
MOS Diode
Load
Transconductance
Grounded Gate
Transconductance
Grounded Source
Class A (Source
or Sink Load)
Class B
(Push-Pull)
Voltage
to Current
Current
to Voltage
Voltage
to Current
Current
to Voltage
Hierarchy
First
Voltage
Stage
Second
Voltage
Stage
Current
Stage
Table 6.1-1
CMOS Analog Circuit Design Page 6.1-9
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Two-Stage CMOS Op Amp
Classical two-stage CMOS op amp broken into voltage-to-current and current-to-voltage stages:
+
- -
+
vin
M1 M2
M3 M4
M5
M6
M7
vout
VDD
VSS
V→I I→V V→I I→V
vout
vin
VBias
Fig. 6.1-8
CMOS Analog Circuit Design Page 6.1-10
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Folded Cascode CMOS Op Amp
Folded cascode CMOS op amp broken into stages.
VSS
VDD
M1 M2
M6
M4
M3
M5
M7
M8
M10
M9
M11
VBias
VBias
VBias
+
-
vin vout
+
-
V→I I→I I→V
vout
vin
Fig. 6.1-9
CMOS Analog Circuit Design Page 6.1-11
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Design of CMOS Op Amps
Steps:
1.) Choosing or creating the basic structure of the op amp.
This step generally is defined by a schematic showing the various transistors and their interconnections.
Generally this diagram does not change throughout the remaining portion of the design unless the
specifications cannot be met and then a new or modified structure must be developed.
2.) Selection of the dc currents and transistor sizes.
Most of the effort of design is in this category.
Simulators are used to aid the designer in this phase (it is important that the design NOT use the
simulator to do design). The general performance of the circuit should be known a priori.
3.) Physical implementation of the design.
Layout of the transistors
Floorplanning the connections, pin-outs, power supply buses and grounds
Extraction of the physical parasitics and resimulation
Verification that the layout is a physical representation of the circuit.
4.) Fabrication
Done by others (take a vacation)
5.) Measurement
Verification of the specifications
Modification of the design as necessary
CMOS Analog Circuit Design Page 6.1-12
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Boundary Conditions and Requirements for CMOS Op Amps
Boundary conditions:
1. Process specification (VT, K', Cox, etc.)
2. Supply voltage and range
3. Supply current and range
4. Operating temperature and range
Requirements:
1. Gain
2. Gain bandwidth
3. Settling time
4. Slew rate
5. Common-mode input range, ICMR
6. Common-mode rejection ratio, CMRR
7. Power-supply rejection ratio, PSRR
8. Output-voltage swing
9. Output resistance
10. Offset
11. Noise
12. Layout area
CMOS Analog Circuit Design Page 6.1-13
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Specifications for a Typical Unbuffered CMOS Op Amp
Boundary Conditions Requirement
Process Specification See Tables 3.1-1 and 3.1-2
Supply Voltage ±2.5 V ±10%
Supply Current 100 μA
Temperature Range 0 to 70°C
Specifications
Gain ≥ 70 dB
Gainbandwidth ≥ 5 MHz
Settling Time ≤ 1 μsec
Slew Rate ≥ 5 V/μsec
Input CMR ≥ ±1.5 V
CMRR ≥ 60 dB
PSRR ≥ 60 dB
Output Swing ≥ ±1.5 V
Output Resistance N/A, capacitive load only
Offset ≤ ±10 mV
Noise ≤ 100nV/ Hz at 1KHz
Layout Area ≤ 10,000 min. channel length2
Some Practical Thoughts on Op Amp Design
CMOS Analog Circuit Design Page 6.1-14
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
1.) Decide upon a suitable topology.
• Experience is a great help
• The topology should be the one capable of meeting most of the specifications
• Try to avoid “inventing” a new topology but start with an existing topology
2.) Determine the type of compensation needed to meet the specifications.
• Consider the load and stability requirements
• Use some form of Miller compensation or a self-compensated approach (shown later)
3.) Design device sizes for proper dc, ac, and transient performance.
• This begins with hand calculations based upon approximate design equations.
• Compensation components are also sized in this step of the procedure.
• After each device is sized by hand, a circuit simulator is used to fine tune the design.†
Two basic steps of design:
1.) “First-cut” - this step is to use hand calculations to propose a design that has potential of satisfying the
specifications. Design robustness is developed in this step.
2.) Optimization - this step uses the computer to refine and optimize the design.
† A useful rule in analog design is: (Use of a simulator)x(Common sense) = Constant. Do not use a simulator for design but for optimization.
CMOS Analog Circuit Design Page 6.2-1
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
SECTION 6.2 - COMPENSATION OF OP AMPS
Compensation
Objective
Objective of compensation is to achieve stable operation when negative feedback is applied around the
op amp.
Types of Compensation
1. Miller - Use of a capacitor feeding back around a high-gain, inverting
stage.
• Miller capacitor only
• Miller capacitor with an unity-gain buffer to block the forward path through the compensation
capacitor. Can eliminate the RHP zero.
• Miller with a nulling resistor. Similar to Miller but with an added series resistance to gain control
over the RHP zero.
2. Self compensating - Load capacitor compensates the op amp (later).
3. Feedforward - Bypassing a positive gain amplifier resulting in phase lead. Gain can be less than unity.
CMOS Analog Circuit Design Page 6.2-2
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Single-Loop, Negative Feedback Systems
A(s)
F(s)
Σ
-
+
Vin(s) Vout(s)
Fig. 6.2-1
A(s) = amplifier gain (normally the differential-mode voltage gain of the op amp)
F(s) = transfer function of the external feedback from the output of the op amp back to the input.
Definitions:
• Open-loop gain = L(s) = -A(s)F(s)
• Closed-loop gain =
Vout(s)
Vin(s) =
A(s)
1+A(s)F(s)
Stability Requirements:
The requirements for stability for a single-loop, negative feedback system is,
|A(jω0°)F(jω0°)| = |L(jω0°)| < 1
where ω0° is defined as
Arg[−A(jω0°)F(jω0°)] = Arg[L(jω0°)] = 0°
Another convenient way to express this requirement is
Arg[−A(jω0dB)F(jω0dB)] = Arg[L(jω0dB)] > 0°
where ω0dB is defined as
|A(jω0dB)F(jω0dB)| = |L(jω0dB)| = 1
CMOS Analog Circuit Design Page 6.2-3
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Illustration of the Stability Requirement using Bode Plots
|A(jω)F(jω)|
0dB
Arg[-A(jω)F(jω)]
180°
135°
90°
45°
0° ω0dB
ω
ω
-20dB/decade
-40dB/decade
ΦM
Frequency (rads/sec.) Fig. 6.2-2
A measure of stability is given by the phase when |A(jω)F(jω)| = 1. This phase is called phase margin.
Phase margin = ΦM = Arg[-A(jω0dB)F(jω0dB)] = Arg[L(jω0dB)]
CMOS Analog Circuit Design Page 6.2-4
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Why Do We Want Good Stability?
Consider the step response of second-order system which closely models the closed-loop gain of the op amp.
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0 5 10 15
45°
50°
55°
60°
65°
vout(t) 70°
Av0
ωot = ωnt (sec.)
Fig. 6.2-3
+
-
A “good” step response is one that quickly reaches its final value.
Therefore, we see that phase margin should be at least 45° and preferably 60° or larger.
(A good rule of thumb for satisfactory stability is that there should be less than three rings.)
Note that good stability is not necessarily the quickest risetime.
CMOS Analog Circuit Design Page 6.2-5
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
The Frequency Response of the Two-Stage Op Amp
Without any compensation, the two-stage op amp can be modeled as shown below.
gmIvin RI gmIIv1 RII CII
v1
+
-
vout
CI
+
-
vin
Fig. 6.2-4
-
+
vin
M1 M2
M3 M4
M5
M6
M7
vout
VDD
VSS
VBias
+
-
CII
CI
The locations for the two poles are given by the following equations
p'1 =
−1
RICI
and
p'2 =
−1
RIICII
where RI (RII) is the resistance to ground seen from the output of the first (second) stage and CI (CII) is the
capacitance to ground seen from the output of the first (second) stage.
CMOS Analog Circuit Design Page 6.2-6
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Frequency Response of the Op Amp
0dB
Avd(0) dB
-20dB/decade
log10(ω)
log10(ω)
180°
90°
Phase Shift
GB
|p1'|
-40dB/decade
45°
135°
-45°/decade
-45°/decade
|p2'|
Arg[A(jω)] |A(jω)|
ω0dB Fig. 6.2-5
0°
Note that the op amp experiences 180° phase shift which will cause poor phase margin in a negative feedback
application.
CMOS Analog Circuit Design Page 6.2-7
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Loop Gain of an Uncompensated Op Amp with Negative Feedback of F(s) = 1 [L(s) = -A(s)]
0dB
Avd(0) dB
-20dB/decade
log10(ω)
log10(ω)
360°
270°
Phase Shift
GB
|p1'|
-40dB/decade
225°
315°
-45°/decade
-45°/decade
|p2'|
Arg[-L(jω)] |L(jω)|
ω0dB Fig. 6.2-5
180°
Note that the phase margin is much less than 45°.
Therefore, the op amp must be compensated before using it in a closed-loop configuration.
CMOS Analog Circuit Design Page 6.2-8
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Miller Compensation of the Two-Stage Op Amp
-
+
vin
M1 M2
M3 M4
M5
M6
M7
vout
VDD
VSS
VBias
+
-
Fig. 6.2-05A
Cc
CI CII
CM
The various capacitors are:
Cc = accomplishes the Miller compensation
CM = capacitance associated with the first-stage mirror (mirror pole)
CI = output capacitance to ground of the first-stage
CII = output capacitance to ground of the second-stage
CMOS Analog Circuit Design Page 6.2-9
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Simplification of the Two-Stage, Small-Signal Frequency Response Model
1.) Assume that gm3 >> gds3 + gds1.
2.) Assume that
gm3
CM
>> GB
Therefore,
-gm1vin
2 CM
1
gm3 gm4v1
gm1vin
2 C1 rds2||rds4
gm6v2 rds6||rds7 CL
v1 v2
Cc
+
-
vout
Fig. 6.2-5B
rds1||rds3
gm1vin rds2||rds4 gm6v2 rds6||rds7
CII
v2
Cc
+
-
CI vout
+
-
vin
CMOS Analog Circuit Design Page 6.2-10
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
General Two-Stage Frequency Response Analysis
where
gmI = gm1 = gm2, RI = rds2||rds4, CI = C1
and
gmII = gm6, RII = rds6||rds7, CII = C2 = CL
Nodal Equations:
-gmIVin = [GI + s(CI + Cc)]V2 - [sCc]Vout and 0 = [gmII - sCc]V2 + [GII + sCII + sCc]Vout
Solving using Cramer’s rule gives,
Vout(s)
Vin(s) =
gmI(gmII°- sCc)
GIGII+s [GII(CI+CII)+GI(CII+Cc)+gmIICc]+s2[CICII+CcCI+CcCII]
=
Ao[1°- s (Cc/gmII)]
1+s [RI(CI+CII)+RII(C2+Cc)+gmIIR1RIICc]+s2[RIRII(CICII+CcCI+CcCII)]
where, Ao = gmIgmIIRIRII
In general, D(s) =

 
  
1 -
s
p1

 
  
1 -
s
p2
= 1 - s

 
  
1
p1
+
1
p2
+
s2
p1p2
→ D(s) ≈ 1 -
s
p1
+
s2
p1p2
, if |p2|>>|p1|
∴ p1 =
-1
RI(CI+CII)+RII(CII+Cc)+gmIIR1RIICc
≈
-1
gmIIR1RIICc
, z =
gmII
Cc
p2 =
-[RI(CI+CII)+RII(CII+Cc)+gmIIR1RIICc]
RIRII(CICII+CcCI+CcCII) ≈
-gmIICc
CICII+CcCI+CcCII
≈
-gmII
CII
where CII > Cc > CI.
gmIVin RI gmIIV2 RII CII
V2
Cc
+
-
Vout CI
+
-
Vin
Fig. 6.2-6
CMOS Analog Circuit Design Page 6.2-11
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Summary of Results for Miller Compensation of the Two-Stage Op Amp
There are three roots of importance:
1.) Right-half plane zero:
z =
gmII
Cc
=
gm6
Cc
This root is very undesirable because it boosts the loop magnitude while decreasing the phase.
2.) Dominant left-half plane pole (the Miller pole):
p1 ≈
-1
gmIIRIRIICc
=
-(gds2+gds4)(gds6+gds7)
gm6Cc
This root accomplishes the desired compensation.
3.) Left-half plane output pole:
p2 ≈
-gmII
CII
≈
-gm6
CL
This pole must be beyond the unity-gainbandwidth or the phase margin will not be satisfied.
Root locus plot of the Miller compensation:
jω
σ
Cc=0
Open-loop poles
Closed-loop poles, Cc≠0
p2 p2' p1' p1 z1 Fig. 6.2-7A
CMOS Analog Circuit Design Page 6.2-12
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Compensated Open-Loop Frequency Response of the Two-Stage Op Amp
0dB
Avd(0) dB
-20dB/decade
log10(ω)
log10(ω)
Phase
Margin
180°
90°
0°
Phase Shift
GB
-40dB/decade
45°
135°
|p1'|
No phase margin
Uncompensated
Compensated
-45°/decade
-45°/decade
|p1| |p2'| |p2|
|A(jω)F(jω)|
Arg[-A(jω)F(jω)|
Compensated
Uncompensated
Fig. 6.2-7B
Note that the unity-gainbandwidth, GB, is
GB = Avd(0)·|p1| = (gmIgmIIRIRII)
1
gmIIRIRIICc
=
gmI
Cc
=
gm1
Cc
=
gm2
Cc
CMOS Analog Circuit Design Page 6.2-13
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Conceptually, where do these roots come from?
1.) The Miller pole:
|p1| ≈
1
RI(gm6RIICc)
2.) The left-half plane output pole:
|p2| ≈
gm6
CII
3.) Right-half plane zero (Zeros always arise from multiple paths from
the input to output):
vout =

 
  
-gm6RII(1/sCc)
RII + 1/sCc
v’ +

 
  
RII
RII + 1/sCc
v’’ =
-RII
 
  
gm6
sCc
- 1
D(s) v
where v = v’ = v’’.
VDD
Cc
RII
vout
vI
M6
RI
≈gm6RIICc
Fig. 6.2-9
VDD
Cc
RII
vout
M6
CII
GB·Cc
1 ≈ 0
VDD
RII
vout
M6
CII
Fig. 6.2-10 VDD
Cc
RII
vout
v'
v''
M6
Fig. 6.2-11
CMOS Analog Circuit Design Page 6.2-14
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Influence of the Mirror Pole
Up to this point, we have neglected the influence of the pole, p3, associated with the current mirror of the
input stage. If |p2| ≈ |p3|, we have problems in compensation. This pole is given approximately as
p3 ≈
-gm3
CM
Fig. 6.2-11A
jω
σ
Open-loop poles
Closed-loop poles
0dB
Avd(0) dB
-6dB/octave
log10(ω)
log10(ω)
Phase
Margin
180°
90°
0°
Phase Shift
GB
-12dB/octave
45°
135°
Cc = 0
-45°/decade
-45°/decade
F = 1
Cc ≠ 0
Cc = 0
Cc ≠ 0
|p1| |p2|
Cc = 0
Cc ≠ 0
|p3|
Excess Phase
due to p3
Roll-off due to p3
-p3
-p2 -p1
Phase margin
due to p3
CMOS Analog Circuit Design Page 6.2-15
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Summary of the Conditions for Stability of the Two-Stage Op Amp
• Unity-gainbandwith is given as:
GB = Av(0)·|p1| = (gmIgmIIRIRII)·

 
  
1
gmIIRIRIICc =
gmI
Cc = (gm1gm2R1R2)·

 
  
1
gm2R1R2Cc =
gm1
Cc
• The requirement for 45° phase margin is:
±180° - Arg[AF] = ±180° - tan-1

    ω |p1| - tan-1

 
  
ω
|p2| - tan-1

 
ωz
= 45°
Let ω = GB and assume that z ≥ 10GB, therefore we get,
±180° - tan-1

 
  
GB
|p1| - tan-1

 
  
GB
|p2| - tan-1

 
GB
z = 45°
135° ≈ tan-1(Av(0)) + tan-1

 
  
GB
|p2| + tan-1(0.1) = 90° + tan-1

 
  
GB
|p2| + 5.7°
39.3° ≈ tan-1

 
  
GB
|p2| ⇒
GB
|p2| = 0.818 ⇒ |p2| ≥ 1.22GB
• The requirement for 60° phase margin:
|p2| ≥ 2.2GB if z ≥ 10GB
• If 60° phase margin is required, then the following relationships apply:
gm6
Cc >
10gm1
Cc ⇒ gm6 > 10gm1 and
gm6
C2 >
2.2gm1
Cc ⇒ Cc > 0.22C2
CMOS Analog Circuit Design Page 6.2-16
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Controlling the Right-Half Plane Zero
Why is the RHP zero a problem?
Because it boosts the magnitude but lags the phase - the worst possible combination for stability.
jω
σ
jω1
jω2
jω3
θ1
θ2 θ3
Fig. 6.2-11B
180° > θ1 > θ2 > θ3
Solution of the problem:
If zeros are caused by two paths to the output, then eliminate one of the paths.
CMOS Analog Circuit Design Page 6.2-17
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Use of Buffer to Eliminate the Feedforward Path through the Miller Capacitor
Inverting
High-Gain
Stage
Ao
Cc
vOUT gmIvin RI
gmIIVI
RII CII
VI
Cc
+
-
CI Vout
+
-
Vin Ro
Ro
AoVout
Fig. 6.2-12
If Ro of the buffer is zero, then the transfer function is given by the following equation,
Vo(s)
Vin(s) =
(gmI)(gmII)(RI)(RII)
1 + s[RICI + RIICII + RICc + gmIIRIRIICc] + s2[RIRIICII(CI + Cc)]
Using the technique as before to approximate p1 and p2 results in the following
p1 ≅
−1
RICI + RIICII + RICc + gmIIRIRIICc
≅
−1
gmIIRIRIICc
and
p2 ≅
−gmIICc
CII(CI + Cc)
Comments:
Poles are approximately what they were before with the zero removed.
For 45° phase margin, |p2| must be greater than GB
For 60° phase margin, |p2| must be greater than 1.73GB
CMOS Analog Circuit Design Page 6.2-18
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Use of Buffer with Finite Output Resistance to Eliminate the RHP Zero
It can be shown that if the output resistance of the buffer amplifier, Ro, is not neglected that a third pole
occurs at,
p4 ≅
−1
Ro[CICc/(CI + Cc)]
and a LHP zero at
z2 ≅
−1
RoCc
Closer examination shows that if a resistor, called a nulling resistor, is placed in series with Cc that the RHP
zero can be eliminated or moved to the LHP.
CMOS Analog Circuit Design Page 6.2-19
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Use of Nulling Resistor to Eliminate the RHP Zero (or turn it into a LHP zero)†
Inverting
High-Gain
Stage
Cc
vOUT
Rz
gmIvin RI
gmIIVI RII CII
Cc
+
-
CI Vout
+
-
Vin
Rz
Fig. 6.2-13
VI
Nodal equations:
gmIVin +
VI
RI
+ sCIVI +

 
  sCc
1 + sCcRz
(VI − Vout) = 0
gmIIVI +
Vo
RII
+ sCIIVout +

 
  
sCc
1 + sCcRz
(Vout − VI) = 0
Solution:
Vout(s)
Vin(s) =
a{1 − s[(Cc/gmII) − RzCc]}
1 + bs + cs2 + ds3
where
a = gmIgmIIRIRII
b = (CII + Cc)RII + (CI + Cc)RI + gmIIRIRIICc + RzCc
c = [RIRII(CICII + CcCI + CcCII) + RzCc(RICI + RIICII)]
d = RIRIIRzCICIICc
† William J. Parrish, "An Ion Implanted CMOS Amplifier for High Performance Active Filters", Ph.D. Dissertation, 1976, Univ. of Calif., Santa
Barbara, CA.
CMOS Analog Circuit Design Page 6.2-20
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Use of Nulling Resistor to Eliminate the RHP - Continued
If Rz is assumed to be less than RI or RII and the poles widely spaced, then the roots of the above transfer
function can be approximated as
p1 ≅
−1
(1 + gmIIRII)RICc
≅
−1
gmIIRIIRICc
p2 ≅
−gmIICc
CICII + CcCI + CcCII
≅
−gmII
CII
p4 =
−1
RzCI
and
z1 =
1
Cc(1/gmII − Rz)
Note that the zero can be placed anywhere on the real axis.
CMOS Analog Circuit Design Page 6.2-21
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Conceptual Illustration of the Nulling Resistor Approach
VDD
Cc
RII
Vout
V'
V''
M6
Rz
Fig. 6.2-14
The output voltage, Vout, can be written as
Vout =
-gm6RII
 
  
Rz +
1
sCc
RII + Rz +
1
sCc
V’ +
RII
RII + Rz +
1
sCc
V” =
-RII
 
  
gm6Rz +
gm6
sCc
- 1
D(s)
Setting the numerator equal to zero and assuming gm6 = gmII gives,
z1 =
1
Cc(1/gmII − Rz)
CMOS Analog Circuit Design Page 6.2-22
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
A Design Procedure that Allows the RHP Zero to Cancel the Output Pole, p2
We desire that z1 = p2 in terms of the previous notation.
Therefore,
1
Cc(1/gmII − Rz) =
−gmII
CII
The value of Rz can be found as
Rz = 
 
  
Cc + CII
Cc
(1/gmII)
With p2 canceled, the remaining roots are p1 and p4(the pole due to Rz) . For unity-gain stability, all that is
required is that
|p4| > Av(0)|p1| =
Av(0)
gmIIRIIRICc
=
gmI
Cc
and
(1/RzCI) > (gmI/Cc) = GB
Substituting Rz into the above inequality and assuming CII >> Cc results in
Cc >
gmI
gmII
CICII
This procedure gives excellent stability for a fixed value of CII (≈ CL).
Unfortunately, as CL changes, p2 changes and the zero must be readjusted to cancel p2.
jω
OA0477
σ
-p4 -p2 -p1 z1
CMOS Analog Circuit Design Page 6.2-23
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Increasing the Magnitude of the Output Pole†
The magnitude of the output pole , p2, can be increased by introducing gain in the Miller capacitor feedback
path. For example,
VDD
VSS
VBias
Cc
M6
M7
M8
M10 M9
M11 M4
vOUT
Iin R1 R2 C2
rds8
gm8Vs8
Cc
V1 Vout
+
-
+
-
+
-
Vs8
Iin R1 R2 C2
gm8Vs8
V1 Vout
+
-
+
-
+
-
Vs8
1
gm8
Cc
gm6V1
gm6V1
Cgd6
Cgd6
Fig. 6.2-15B
The resistors R1 and R2 are defined as
R1 =
1
gds2 + gds4 + gds9
and R2 =
1
gds6 + gds7
where transistors M2 and M4 are the output transistors of the first stage.
Nodal equations:
Iin = G1V1 - gm8Vs8 = G1V1 -

 
  
gm8sCc
gm8 + sCc
Vout and 0 = gm6V1 +

 
  
G2 + sC2 +
gm8sCc
gm8 + sCc
Vout
† B.K. Ahuja, “An Improved Frequency Compensation Technique for CMOS Operational Amplifiers,” IEEE J. of Solid-State Circuits, Vol. SC-18,
No. 6 (Dec. 1983) pp. 629-633.
CMOS Analog Circuit Design Page 6.2-24
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Increasing the Magnitude of the Output Pole - Continued
Solving for the transfer function Vout/Iin gives,
Vout
Iin
=

 
  
-gm6
G1G2

  
   
  
  
1 +
sCc
gm8
1 + s

 
  
Cc
gm8
+
C2
G2
+
Cc
G2
+
gm6Cc
G1G2
+ s2

 
  
CcC2
gm8G2
Using the approximate method of solving for the roots of the denominator illustrated earlier gives
p1 =
-1
Cc
gm8
+
Cc
G2
+
C2
G2
+
gm6Cc
G1G2
≈
-6
gm6rds
2Cc
and
p2 ≈
-
gm6rds
2Cc
6
CcC2
gm8G2
=
gm8rds
2G2
6

 
  
gm6
C2
= 
 
  
gm8rds
3 |p2’|
where all the various channel resistance have been assumed to equal rds and p2’ is the output pole for normal
Miller compensation.
Result:
Dominant pole is approximately the same and the output pole is increased by roughly gmrds.
CMOS Analog Circuit Design Page 6.2-25
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Increasing the Magnitude of the Output Pole - Continued
In addition there is a LHP zero at -gm8/sCc and a RHP zero due to Cgd6 (shown dashed in the model on Page
6.2-23) at gm6/Cgd6.
Roots are:
jω
σ
gm6
Cgd6
-gm8
Cc
-gm6gm8rds
3C2
-1
gm6rdsCc Fig. 6.2-16A
CMOS Analog Circuit Design Page 6.2-26
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Concept Behind the Increasing of the Magnitude of the Output Pole
VDD
Cc
rds7
vout
M6 CII
GB·Cc
1 ≈ 0
VDD
vout
M6
CII
M8
gm8rds8
Fig. 6.2-16
rds7
3
Rout = rds7||

 
  
3
gm6gm8rds8
≈
3
gm6gm8rds8
Therefore, the output pole is approximately,
|p2| ≈
gm6gm8rds8
3CII
CMOS Analog Circuit Design Page 6.2-27
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Feedforward Compensation
Use two parallel paths to achieve a LHP zero for lead compensation purposes.
Cc
A
Vi Vout
Inverting
High Gain
Amplifier
CII RII
RHP Zero Cc
-A
Vi Vout
Inverting
High Gain
Amplifier
CII RII
LHP Zero
A
Vi CII RII Vout
Cc
gmIIVi
+
-
+
- Fig. 6.2-17
Cc
Vi Vout +A
Vout(s)
Vin(s) =
ACc
Cc + CII

 
  
s + gmII/ACc
s + 1/[RII(Cc + CII)]
To use the LHP zero for compensation, a compromise must be observed.
• Placing the zero below GB will lead to boosting of the loop gain which could deteriorate the phase margin.
• Placing the zero above GB will have less influence on the leading phase caused by the zero.
Note that a source follower is a good candidate for the use of feedforward.
CMOS Analog Circuit Design Page 6.2-28
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Self-Compensated Op Amps
Self compensation occurs when the load capacitor is the compensation capacitor (can never be unstable for
resistive feedback)
OA048
-
+
vin vout
CL
+
-
Gm
Rout(must be large)
Increasing CL
|dB|
Av(0) dB
0dB ω
Rout
-20dB/dec.
Voltage gain:
vout
vin
= Av(0) = GmRout
Dominant pole:
p1 =
-1
RoutCL
Unity-gainbandwidth:
GB = Av(0)·|p1| =
Gm
CL
Stability:
Large load capacitors simply reduce the GB and the phase is 90° at the unity gain frequency
CMOS Analog Circuit Design Page 6.2-29
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Slew Rate of a Two-Stage Op Amp
Remember that slew rate occurs when currents flowing in a capacitor become limited and is given as
Ilim = C
dvC
dt where vC is the voltage across the capacitor C.
-
+ v
in>>0
M1 M2
M3 M4
M5
M6
M7
vout
VDD
VSS
VBias
+
-
Cc
CL
I5
Assume a
virtural
ground
I7
I5 I6 ICL
Positive Slew Rate
-
+ v
in<<0
M1 M2
M3 M4
M5
M6
M7
vout
VDD
VSS
VBias
+
-
Cc
CL
I5
Assume a
virtural
ground
I7
I I6=0 5 ICL
Negative Slew Rate Fig. 6.2-18
SR+ = min

 
  
I5
Cc
,
I6-I5-I7
CL
=
I5
Cc
because I6>>I5 SR- = min

 
  
I5
Cc
,
I7-I5
CL
=
I5
Cc
if I7>>I5.
Therefore, if CL is not too large and if I7 is significantly greater than I5, then the slew rate of the two-stage op
amp should be,
SR =
I5
Cc
CMOS Analog Circuit Design Page 6.3-1
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
SECTION 6.3 - TWO-STAGE OP AMP DESIGN
Unbuffered, Two-Stage CMOS Op Amp
-
+
vin
M1 M2
M3 M4
M5
M6
M7
vout
VDD
VSS
VBias
+
-
Cc
CL
Fig. 6.3-1
Notation:
Si =
Wi
Li
= W/L of the ith transistor
CMOS Analog Circuit Design Page 6.3-2
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
DC Balance Conditions for the Two-Stage Op Amp
For best performance, keep all transistors in saturation.
M4 is the only transistor that cannot be forced into saturation
by internal connections or external voltages.
Therefore, we develop conditions to force M4 to be in
saturation.
1.) First assume that VSG4 = VSG6. This will cause “proper
mirroring” in the M3-M4 mirror. Also, the gate and drain of
M4 are at the same potential so that M4 is “guaranteed” to
be in saturation.
2.) If VSG4 = VSG6, then I6 =

 
  
S6
S4
I4
3.) However, I7 =

    S7
S5
I5 =

 
  
S7
S5
(2I4)
4.) For balance, I6 must equal I7 ⇒
S6
S4
=
2S7
S5
which is called the “balance conditions”
5.) So if the balance conditions are satisfied, then VDG4 = 0 and M4 is saturated.
-
+
vin
M1 M2
M3 M4
M5
M6
M7
vout
VDD
VSS
VBias
+
-
Cc
CL
-
V + SG6
-
V + SG4
I4
I5
I7
I6
Fig. 6.3-1A
CMOS Analog Circuit Design Page 6.3-3
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Design Relationships for the Two-Stage Op Amp
Slew rate SR =
I5
Cc
(Assuming I7 >>I5 and CL > Cc)
First-stage gain Av1 =
gm1
gds2 + gds4
=
2gm1
I5(λ2 + λ4)
Second-stage gain Av2 =
gm6
gds6 + gds7
=
gm6
I6(λ6 + λ7)
Gain-bandwidth GB =
gm1
Cc
Output pole p2 =
−gm6
CL
RHP zero z1 =
gm6
Cc
60° phase margin requires that gm6 = 2.2gm2(CL/Cc) if all other roots are ≥ 10GB.
Positive ICMR Vin(max) = VDD −
I5
β3
− |VT03|(max) + VT1(min))
Negative ICMR Vin(min) = VSS +
I5
β1
+ VT1(max) + VDS5(sat)
Saturation voltageVDS(sat) =
2IDS
β
It is assumed that all transistors are in saturation for the above relationships.
CMOS Analog Circuit Design Page 6.3-4
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Op Amp Specifications
The following design procedure assumes that specifications for the following parameters are given.
1. Gain at dc, Av(0)
2. Gain-bandwidth, GB
3. Phase margin (or settling time)
4. Input common-mode range, ICMR
5. Load Capacitance, CL
6. Slew-rate, SR
7. Output voltage swing
8. Power dissipation, Pdiss
-
+
vin M1 M2
M3 M4
M5
M6
M7
vout
VDD
VSS
VBias
+
-
Cc
CL
VSG4
+
-
Max. ICMR
and/or p3
VSG6
+
-
I6
gm6 and
VSG4=VSG6 or
Vout(max)
Cc ≈ 0.2CL
(PM = 60°)
GB =
gm1
Cc
Min. ICMR I5 I5 = SR·Cc Vout(min)
Fig. 6.3-2A
CMOS Analog Circuit Design Page 6.3-5
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Unbuffered Op Amp Design Procedure
This design procedure assumes that the gain at dc (Av), unity gain bandwidth (GB), input common mode
range (Vin(min) and Vin(max)), load capacitance (CL), slew rate (SR), settling time (Ts), output voltage swing
(Vout(max) and Vout(min)), and power dissipation (Pdiss) are given. Choose the smallest device length which
will keep the channel modulation parameter constant and give good matching for current mirrors.
1. From the desired phase margin, choose the minimum value for Cc, i.e. for a 60° phase margin we use the
following relationship. This assumes that z ≥ 10GB.
Cc > 0.22CL
2. Determine the minimum value for the “tail current” (I5) from the largest of the two values.
I5 = SR .Cc or I5 ≅ 10

 
  
VDD + |VSS|
2 .Ts
3. Design for S3 from the maximum input voltage specification.
S3 =
2I3
K'3[VDD − Vin(max) − |VT03|(max) + VT1(min)]2 ≥ 1
4. Verify that the pole of M3 due to Cgs3 and Cgs4 (=0.67W3L3Cox) will not be dominant by assuming it to be
greater than 10 GB
gm3
2Cgs3
> 10GB.
5. Design for S1 (S2) to achieve the desired GB.
gm1 = GB . Cc ⇒ S1 = S2 =
gm1
K'1I5
CMOS Analog Circuit Design Page 6.3-6
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Unbuffered Op Amp Design Procedure - Continued
6. Design for S5 from the minimum input voltage. First calculate VDS5(sat) then find S5.
VDS5(sat) = Vin(min) − VSS −
I5
β1
− VT1(max) ≥ 100 mV → S5 =
2I5
K'5[VDS5(sat)]2
7. Find S6 by letting the second pole (p2) be equal to 2.2 times GB and assuming that VSG4 = VSG6.
gm6 = 2.2gm2(CL/Cc) → S6 = S4
gm6
gm4
8. Calculate I6 from
I6 =
gm6
2
2K'6S6
Check to make sure that S6 satisfies the Vout(max) requirement and adjust as necessary.
9. Design S7 to achieve the desired current ratios between I5 and I6.
S7 = (I6/I5)S5 (Check the minimum output voltage requirements)
10.Check gain and power dissipation specifications.
Av =
2gm2gm6
I5(λ2 + λ3)I6(λ6 + λ7) Pdiss = (I5 + I6)(VDD + |VSS|)
11.If the gain specification is not met, then the currents, I5 and I6, can be decreased or the W/L ratios of M2
and/or M6 increased. The previous calculations must be rechecked to insure that they are satisfied. If the
power dissipation is too high, then one can only reduce the currents I5 and I6. Reduction of currents will
probably necessitate increase of some of the W/L ratios in order to satisfy input and output swings.
12. Simulate the circuit to check to see that all specifications are met.
CMOS Analog Circuit Design Page 6.3-7
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Example 6.3-1 - Design of a Two-Stage Op Amp
Using the material and device parameters given in Tables 3.1-2 and 3.2-1, design an amplifier similar to
that shown in Fig. 6.3-1 that meets the following specifications. Assume the channel length is to be 1μm.
Av > 5000V/V VDD = 2.5V VSS = -2.5V 60° phase margin
GB = 5MHz CL = 10pF SR > 10V/μs
Vout range = ±2V ICMR = -1 to 2V Pdiss ≤ 2mW
Solution
1.) The first step is to calculate the minimum value of the compensation capacitor Cc, which is
Cc > (2.2/10)(10 pF) = 2.2 pF
2.) Choose Cc as 3pF. Using the slew-rate specification and Cc calculate I5.
I5 = (3x10-12)(10 x 106) = 30 μA
3.) Next calculate (W/L)3 using ICMR requirements.
(W/L)3 =
30 x 10-6
(50x10-6)[2.5 − 2 − 0.85 + 0.55]2 = 15 → (W/L)3 = (W/L)4 = 15
4.) Now we can check the value of the mirror pole, p3, to make sure that it is in fact greater than 10GB.
Assume the Cox = 0.4fF/μm2. The mirror pole can be found as
p3 ≈
-gm3
2Cgs3
=
- 2K’pS3I3
2(0.667)W3L3Cox
= 2.81x109(rads/sec)
or 448 MHz. Thus, p3, is not of concern in this design because p3 >> 10GB.
CMOS Analog Circuit Design Page 6.3-8
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Example 6.3-1 - Continued
5.) The next step in the design is to calculate gm1 to get
gm1 = (5x106)(2π)(3x10-12) = 94.25μS
Therefore, (W/L)1 is
(W/L)1 = (W/L)2 =
gm1
2
2K’NI1
=
(94.25)2
2·110·15 = 2.79 ≈ 3.0⇒ (W/L)1 = (W/L)2 = 3
6.) Next calculate VDS5,
VDS5 = (−1) − (−2.5) −
30x10-6
110x10-6·3 - .85 = 0.35V
Using VDS5 calculate (W/L)5 from the saturation relationship.
(W/L)5 =
2(30 x 10-6)
(110 x 10-6)(0.35)2 = 4.49 ≈ 4.5 → (W/L)5 = 4.5
7.) For 60° phase margin, we know that
gm6 ≥ 10gm1 ≥ 942.5μS
Assuming that gm6 = 942.5μS and knowing that gm4 = 150μS, we calculate (W/L)6 as
(W/L)6 = 15
942.5 x 10-6
(150 x 10-6) = 94.25 ≈ 94
CMOS Analog Circuit Design Page 6.3-9
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Example 6.3-1 - Continued
8.) Calculate I6 using the small-signal gm expression: I6 =
(942.5 x 10-6)2
(2)(50 x 10-6)(94) = 94.5μA ≈ 95μA
If we calculate (W/L)6 based on Vout(max), the value is approximately 15. Since 94 exceeds the specification
and maintains better phase margin, we will stay with (W/L)6 = 94 and I6 = 95μA.
With I6 = 95μA the power dissipation is
Pdiss = 5V·(30μA+95μA) = 0.625mW.
9.) Finally, calculate (W/L)7
(W/L)7 = 4.5 

 
95 x 10-6
30 x 10-6 = 14.25 ≈ 14 → (W/L)7 = 14
Let us check the Vout(min) specification although the W/L of M7 is so large that this is probably not
necessary. The value of Vout(min) is
Vout(min) = VDS7(sat) =
2·95
110·14 = 0.351V
which is less than required. At this point, the first-cut design is complete.
10.) Now check to see that the gain specification has been met
Av =
(94.25 x 10-6)(942.5 x 10-6)
15 x 10-6(.04 + .05)95 x 10-6(.04 + .05) = 7,696V/V
which meets specifications. An easy way to increase the gain would be to increase the W and L values by a
factor of two which because of the decreased value of λ would multiply the above gain by a factor of 20.
CMOS Analog Circuit Design Page 6.3-10
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Example 6.3-1 - Continued
The final step in the hand design is to establish true electrical widths and lengths based upon ΔL and
ΔW variations. In this example ΔL will be due to lateral diffusion only. Unless otherwise noted, ΔW will not
be taken into account. All dimensions will be rounded to integer values. Assume that ΔL = 0.2μm.
Therefore, we have
W1 = W2 = 3(1 − 0.4) = 1.8 μm ≈ 2μm
W3 = W4 = 15(1 − 0.4) = 9μm
W5 = 4.5(1 - 0.4) = 2.7μm ≈ 3μm
W6 = 94(1 - 0.4) = 56.4μm ≈ 56μm
W7 = 14(1 - 0.4) = 8.4 ≈ 8μm
The figure below shows the results of the first-cut design. The W/L ratios shown do not account for the
lateral diffusion discussed above. The next phase requires simulation.
-
+
vin
M1 M2
M3 M4
M5
M6
M7
vout
VDD = 2.5V
VSS = -2.5V
Cc = 3pF
CL =
10pF
3μm
1μm
3μm
1μm
15μm
1μm
15μm
1μm
M8
4.5μm
1μm
30μA
4.5μm
1μm
14μm
1μm
94μm
1μm
30μA
95μA
Fig. 6.3-3
CMOS Analog Circuit Design Page 6.3-11
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Incorporating the Nulling Resistor into the Miller Compensated Two-Stage Op Amp
Circuit:
VDD
VSS
IBias
CL
CM Cc vout
VB
VA
M1 M2
M3 M4
M5
M6
M7
M9
M10
M11
M12
vin- vin+
M8
Fig. 6.3-4
VC
We saw earlier that the roots were:
p1 = −
gm2
AvCc
= −
gm1
AvCc
p2 = −
gm6
CL
p4 = −
1
RzCI
z1 =
−1
RzCc − Cc/gm6
where Av = gm1gm6RIRII. (Note that p4 is the pole resulting from the nulling resistor compensation technique.)
CMOS Analog Circuit Design Page 6.3-12
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Design of the Nulling Resistor (M8)
In order to place the zero on top of the second pole (p2), the following relationship must hold
Rz =
1
gm6

 
  
CL + Cc
Cc
=

 
  
Cc+CL
Cc
1
2K’PS6I6
The resistor, Rz, is realized by the transistor M8 which is operating in the active region because the dc current
through it is zero. Therefore, Rz, can be written as
Rz =
dvDS8
diD8

VDS8=0
=
1
K’PS8(VSG8-|VTP|)
The bias circuit is designed so that voltage VA is equal to VB.
∴ |VGS10| − |VT| = |VGS8| − |VT| ⇒ VSG11 = VSG6 ⇒ 


  
W11
L11
=

 
  
I10
I6

 
  
W6
L6
In the saturation region
|VGS10| − |VT| =
2(I10)
K'P(W10/L10) = |VGS8| − |VT|
∴ Rz =
1
K’PS8
K’PS10
2I10
=
1
S8
S10
2K’PI10
Equating the two expressions for Rz gives
  
  
W8
L8
=

 
  
Cc
CL + Cc
S10S6I6
I10
CMOS Analog Circuit Design Page 6.3-13
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Example 6.3-2 - RHP Zero Compensation
Use results of Ex. 6.3-1 and design compensation circuitry so that the RHP zero is moved from the
RHP to the LHP and placed on top of the output pole p2. Use device data given in Ex. 6.3-1.
Solution
The task at hand is the design of transistors M8, M9, M10, M11, and bias current I10. The first step in
this design is to establish the bias components. In order to set VA equal to VB, thenVSG11 must equal VSG6.
Therefore,
S11 = (I11/I6)S6
Choose I11 = I10 = I9 = 15μA which gives S11 = (15μA/95μA)94 = 14.8 ≈ 15.
The aspect ratio of M10 is essentially a free parameter, and will be set equal to 1. There must be
sufficient supply voltage to support the sum of VSG11, VSG10, and VDS9. The ratio of I10/I5 determines the
(W/L) of M9. This ratio is
(W/L)9 = (I10/I5)(W/L)5 = (15/30)(4.5) = 2.25 ≈ 2
Now (W/L)8 is determined to be
(W/L)8 = 

 
3pF
3pF+10pF
1·94·95μA
15μA = 5.63 ≈ 6
CMOS Analog Circuit Design Page 6.3-14
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Example 6.3-2 - Continued
It is worthwhile to check that the RHP zero has been moved on top of p2. To do this, first calculate the
value of Rz. VSG8 must first be determined. It is equal to VSG10, which is
VSG10 =
2I10
K’PS10
+ |VTP| =
2·15
50·1 + 0.7 = 1.474V
Next determine Rz.
Rz =
1
K’PS8(VSG10-|VTP|) =
106
50·5.63(1.474-.7) = 4.590kΩ
The location of z1 is calculated as
z1 =
−1
(4.590 x 103)(3x10-12) −
3x10-12
942.5x10-6
= -94.46x106 rads/sec
The output pole, p2, is
p2 =
942.5x10-6
10x10-12 = -94.25x106 rads/sec
Thus, we see that for all practical purposes, the output pole is canceled by the zero that has been moved
from the RHP to the LHP.
The results of this design are summarized below.
W8 = 6 μm W9 = 2 μm W10 = 1 μm W11 = 15 μm
CMOS Analog Circuit Design Page 6.3-15
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
An Alternate Form of Nulling Resistor
To cancel p2,
z1 = p2 → Rz =
Cc+CL
gm6ACC
=
1
gm6B
Which gives
gm6B = gm6A
 
  
Cc
Cc+CL
In the previous example,
gm6A = 942.5μS, Cc = 3pF and CL = 10pF.
Choose I6B = 10μA to get
gm6B =
gm6ACc
Cc + CL →
2KPW6BI6B
L6B
=

 
  
Cc
Cc+CL
2KPW6AID6
L6A
or
W6B
L6B
= 

 
3
13
2
I6A
I6B
W6A
L6A
= 

 
3
13
2


 
95
10 (94) = 47.6 → W6B = 48μm
-
+
vin
M1 M2
M3 M4
M5
M6
M7
vout
VDD
VSS
VBias
+
-
Cc
CL
M11 M10
M6B
M8 M9
Fig. 6.3-4A
CMOS Analog Circuit Design Page 6.3-16
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Programmability of the Two-Stage Op Amp
The following relationships depend on the bias current, Ibias, in the
following manner and allow for programmability after fabrication.
Av(0) = gmIgmIIRIRII ∝
1
IBias
GB =
gmI
Cc
∝ IBias
Pdiss = (VDD+|VSS|)(1+K1+K2)IBias ∝ Ibias
SR =
K1IBias
Cc
∝ IBias
Rout =
1
2λK2IBias
∝
1
IBias
|p1| =
1
gmIIRIRIICc
∝
IBias
2
IBias
∝ IBias
1.5
|z| =
gmII
Cc
∝ IBias
Illustration of the Ibias dependence →
-
+
vin
M1 M2
M3 M4
M5
M6
M7
vout
VDD
VSS
IBias
Fig. 6.3-04D
K1IBias
K2IBias
103
102
100
101
10-1
10-2
10-3
1 10 100
IBias
IBias(ref)
Pdiss and SR |p1|
GB and z
Ao and Rout
Fig. 6.3-4E
CMOS Analog Circuit Design Page 6.3-17
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Simulation of the Electrical Design
Area of source or drain = AS = AD = W[L1 + L2 + L3]
where
L1 = Minimum allowable distance between the contact in the S/D and the polysilicon (5μm)
L2 = Width of a minimum size contact (5μm)
L3 = Minimum allowable distance from the contact in S/D to the edge of the S/D (5μm)
∴ AS = AD = Wx15μm
Perimeter of the source or drain = PD = PS = 2W + 2(L1+L2+L3)
∴ PD = PS = 2W + 30μm
Illustration:
Poly
Diffusion Diffusion
L
W
L3 L2 L1 L1 L2 L3
Fig. 6.3-5
CMOS Analog Circuit Design Page 6.3-18
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
5-to-1 Current Mirror with Different Physical Performances
Input
Output
Ground
Input
Output
Ground
(a)
(b)
Figure 6.3-6 The layout of a 5-to-1 current mirror. (a) Layout which minimizes
area at the sacrifice of matching. (b) Layout which optimizes matching.
Metal 1
Poly
Diffusion
Contacts
CMOS Analog Circuit Design Page 6.3-19
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
1-to-1.5 Transistor Matching
Figure 6.3-7 The layout of two transistors with a 1.5 to 1 matching using
centroid geometry to improve matching.
Gate 2
Drain 2
Source 2
Gate 1
Drain 1
Source 1
Metal 2 Metal 1 Poly Diffusion Contacts
2 1 2 1 2
CMOS Analog Circuit Design Page 6.3-20
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Reduction of Parasitics
The major objective of good layout is to minimize the parasitics that influence the design.
Typical parasitics include:
Capacitors to ac ground
Series resistance
Capacitive parasitics is minimized by minimizing area and maximizing the distance between the conductor and
ac ground.
Resistance parasitics are minimized by using wide busses and keeping the bus length short.
For example:
At 2mΩ/square, a metal run of 1000μm and 2μm wide will have 1Ω of resistance.
At 1 mA this amounts to a 1 mV drop which could easily be greater than the least significant bit of an
analog-digital converter. (For example, a 10 bit ADC with VREF = 1V has an LSB of 1mV)
CMOS Analog Circuit Design Page 6.3-21
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Technique for Reducing the Overlap Capacitance
Square Donut Transistor:
Source
Drain
Source
Gate
Source
Source
Figure 6.3-8 Reduction of Cgd by a donut shaped transistor.
Metal 1
Poly
Diffusion
Contacts
Note: Can get more W/L in less area with the above geometry.
CMOS Analog Circuit Design Page 6.3-22
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Chip Voltage Bias Distribution Scheme
+
-
Rext
VDD
Bandgap
Voltage,
VBG
M7
M5
M4
M1
Q1 Q2
M2
M3
M6
M8 M9
M10
M11
M12
Q3
IPTAT R1 R2
M13
M14
M15
M16
xn
IREF
R3
R4
Figure 6.3-9 Generation of a reference voltage which is distributed on the chip
as a current to slave bias circuits.
VDD
VPBias1
VPBias2
VNBias2
VNBias1
Remote portion of chip
M2A M4A
M3A
Location of reference voltage
Slave
Bias
Circuit
M5A
M6A
R2A
R1A
M1A
Master
Voltage
Reference
Circuit
CMOS Analog Circuit Design Page 6.4-1
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
SECTION 6.4 - PSRR OF THE TWO-STAGE OP AMP
What is PSRR?
PSRR =
Av(Vdd=0)
Add(Vin=0)
How do you calculate PSRR?
You could calculate Av and Add and divide.
+
- VDD
VSS
Vdd
Vout
V2
V1
V2
V1
Av(V1-V2)
Vss ±AddVdd
Vout
Fig. 6.4-1
Vout = AddVdd + Av(V1-V2) = AddVdd - AvVout → Vout(1+Av) = AddVdd
∴
Vout
Vdd
=
Add
1+Av
≈
Add
Av
=
1
PSRR+ (Good for frequencies up to GB)
+
- VDD
VSS
Vdd
V2
V1
Vss
Vout Vin
Fig. 6.4-1A
CMOS Analog Circuit Design Page 6.4-2
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Positive PSRR of the Two-Stage Op Amp
M1 M2
M3 M4
M5
M6
M7
Vout
VDD
VSS
VBias
Cc
CII
Vdd
CI
gm1V5
rds1
gm1Vout
rds2
gm6(V1-Vdd)
gm2V5
rds5
gm3
1 I3 rds4
I3
rds6
Vout
CI rds7
Cc
CII
+
-
V1
+
-
Vdd
Vdd
I3
gm3
-
Fig. 6.4-2
+ V5 -
gm1Vout
rds2
gm6(V1-Vdd)
rds4 rds6
CI Vout rds7
Cc
CII
+
-
V1
+
-
Vdd
-
gds1Vdd
-
V5 ≈ 0
The nodal equations are:
(gds1 + gds4)Vdd = (gds2 + gds4 + sCc + sCI)V1 − (gm1 + sCc)Vout
(gm6 + gds6)Vdd = (gm6 − sCc)V1 + (gds6 + gds7 + sCc + sCII)Vout
Using the generic notation the nodal equations are:
GIVdd = (GI + sCc + sCI)V1 − (gmI + sCc)Vout
(gmII + gds6)Vdd = (gmII − sCc)V1 + (GII + sCc + sCII)Vout
whereGI = gds1 + gds4 = gds2 + gds4, GII = gds6 + gds7, gmI = gm1 = gm2 and gmII = gm6
CMOS Analog Circuit Design Page 6.4-3
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Positive PSRR of the Two-Stage Op Amp - Continued
Using Cramers rule to solve for the transfer function,Vout/Vdd, and inverting the transfer function gives the
following result.
Vdd
Vout
=
s2[CcCI+CICII + CIICc]+ s[GI(Cc+CII) + GII(Cc+CI) + Cc(gmII − gmI)] + GIGII+gmIgmII
s[Cc(gmII+GI+gds6) + CI(gmII + gds6)] + GIgds6
We may solve for the approximate roots of numerator as
PSRR+ =
Vdd
Vout
≅

 
  
gmIgmII
GIgds6

 
   

 
  
sCc
gmI
+ 1 
 
  
s(CcCI+CICII+CcCII)
gmII Cc
+ 1
  
  
sgmIICc
GIgds6
+ 1
where gmII > gmI and that all transconductances are larger than the channel conductances.
∴ PSRR+ =
Vdd
Vout
=

 
  
gmIgmII
GIgds6

  
   
  
  
sCc
gmI + 1

 
  
sCII
gmII
+ 1
sgmIICc
GIgds6
+ 1
=

 
  
GIIAvo
gds6


 
s
GB + 1

 
  
s
|p2| + 1
  
  
sGIIAvo
gds6GB + 1
CMOS Analog Circuit Design Page 6.4-4
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Positive PSRR of the Two-Stage Op Amp - Continued
|PSRR+(jω)| dB
GIIAv0
0
gds6GB
GIIAv0
GB |p2|
ω
Fig. 6.4-3
gds6
At approximately the dominant pole, the PSRR falls off with a -20dB/decade slope and degrades the higher
frequency PSRR + of the two-stage op amp.
Using the values of Example 6.3-1 we get:
PSRR+(0) = 68.8dB, z1 = -5MHz, z2 = -15MHz and p1 = -906Hz
CMOS Analog Circuit Design Page 6.4-5
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Concept of the PSRR+ for the Two-Stage Op Amp
M1 M2
M3 M4
M5
M6
M7
Vout
VDD
VSS
VBias
Cc
CII
Vdd
CI
Fig. 6.4-3A
Cc
Vdd Rout
Vout
Other sources
of PSRR+
besides Cc
1
RoutCc ω
Vout
Vdd
0dB
1.) The M7 current sink causes VSG6 to act like a battery.
2.) Therefore, Vdd couples from the source to gate of M6.
3.) The path to the output is through any capacitance from gate to drain of M6.
Conclusion:
The Miller capacitor Cc couples the positive power supply ripple directly to the output.
Must reduce or eliminate Cc.
CMOS Analog Circuit Design Page 6.4-6
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Negative PSRR of the Two-Stage Op Amp withVBias Grounded
M1 M2
M3 M4
M5
M6
M7
Vout
VDD
VSS
VBias
Cc
CII
Vss
CI
Fig. 6.4-4A
gmIVout
RI CI
gmIIV1
CII RII
gm7Vss
+
-
Vout
Cc
VBias grounded
Nodal equations for VBias grounded:
0 = (GI + sCc+sCI)V1 - (gmI+sCc)Vo
gm7Vss = (gMII-sCc)V1 + (GII+sCc+sCII)Vo
Solving for Vout/Vss and inverting gives
Vss
Vout
=
s2[CcCI+CICII+CIICc] + s[GI(Cc+CII) + GII(Cc+CI) + Cc(gmII − gmI)] + GIGII + gmIgmII
[s(Cc+CI)+GI]gm7
CMOS Analog Circuit Design Page 6.4-7
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Negative PSRR of the Two-Stage Op Amp withVBias Grounded - Continued
Again using the technique described previously, we may solve for the approximate roots as
PSRR- =
Vss
Vout
≅

 
  
gmIgmII
GIgm7

 
   

 
  
sCc
gmI
+ 1 
 
  
s(CcCI+CICII+CcCII)
gmII Cc
+ 1
  
  
s(Cc+CI)
GI
+ 1
This equation can be rewritten approximately as
PSRR- =
Vss
Vout
≅

 
  
gmIgmII
GIgm7

 
   

 
  
sCc
gmI
+ 1

 
  
sCII
gmII + 1
  
  
sCc
GI
+ 1
=

 
  
GIIAv0
gm7

 
   
 
 
s
GB + 1

 
  
s
|p2| +1
  
  
s
GB
gmI
GI
+1
Comments:
PSRR- zeros = PSRR + zeros
DC gain ≈ Second-stage gain,
PSRR- pole ≈ (Second-stage gain) x (PSRR+ pole)
Assuming the values of Ex. 6.3-1 gives a gain of 23.7 dB and a pole -147 kHz. The dc value of PSRR- is
very poor for this case, however, this case can be avoided by correctly implementing VBias which we consider
next.
CMOS Analog Circuit Design Page 6.4-8
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Negative PSRR of the Two-Stage Op Amp withVBias Connected to VSS
M1 M2
M3 M4
M5
M6
M7
Vout
VDD
VSS
VBias
Cc
CII
Vss
CI
Fig. 6.4-4B
rds5
rds6 Vout
rds7
CI
Cc
Cgd7
+
-
V1
+
-
Vss
gmIVout
RI gmIIV1
VBias connected to VSS
CII
If the value of VBias is independent of Vss, then the model shown results. The nodal equations for this model
are
0 = (GI + sCc + sCI)V1 - (gmI + sCc)Vout
and
(gds7 + sCgd7)Vss = (gmII - sCc)V1 + (GII + sCc + sCII + sCgd7)Vout
Again, solving for Vout/Vss and inverting gives
Vss
Vout
=
s2[CcCI+CICII+CIICc+CICgd7+CcCgd7]+s[GI(Cc+CII+Cgd7)+GII(Cc+CI)+Cc(gmII−gmI)]+GIGII+gmIgmII
(sCgd7°+ gds7)(s(CI+Cc) + GI)
CMOS Analog Circuit Design Page 6.4-9
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Negative PSRR of the Two-Stage Op Amp withVBias Connected to VSS - Continued
Assuming that gmII > gmI and solving for the approximate roots of both the numerator and denominator
gives
PSRR- =
Vss
Vout
≅

 
  
gmIgmII
GIgds7

 
   

 
  
sCc
gmI
+ 1 
 
  
s(CcCI+CICII+CcCII)
gmII Cc
+ 1
  
  
sCgd7
gds7
+1

 
  
s(CI+Cc)
GI
+ 1
This equation can be rewritten as
PSRR- =
Vss
Vout
≈

 
  
GIIAv0
gds7

 
   
 
 
s
GB + 1

 
  
s
|p2| +1

 
  
sCgd7
gds7
+1

 
  
sCc
GI
+ 1
Comments:
• DC gain has been increased by the ratio of GII to gds7
• Two poles instead of one, however the pole at -gds7/Cgd7 is very large and can be ignored.
Using the values of Ex. 6.3-1 and assume that Cds7 = 10fF, gives,
PSRR-(0) = 76.7dB
Poles at -71.2kHz and -149MHz
CMOS Analog Circuit Design Page 6.4-10
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Frequency Response of the Negative PSRR of the Two-Stage Op Amp with VBias Connected to VSS
|PSRR-(jω)| dB
GIIAv0
0
GB |p2|
ω
Fig. 6.4-5
gds7
GI
Cc
Invalid
region
of
analysis
CMOS Analog Circuit Design Page 6.4-11
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Approximate Model for Negative PSRR with VBias Connected to Ground
M1 M2
M3 M4
M5
M6
M7
Vout
VDD
VSS
VBias
Cc
CII
Vss
CI
Fig. 6.4-6A
VBias grounded
VSS
Vss
VBias
iss M5 or M7
Path through the input stage is not important as long as
the CMRR is high.
Path through the output stage:
vout ≈ issZout = gm7ZoutVss
∴
Vout
Vss
= gm7Zout = gm7Rout

 
  
1
sRoutCout+1
Vss
20 to
40dB
Vout
0dB
RoutCout
1 ω
Fig.6.4-7A
CMOS Analog Circuit Design Page 6.4-12
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Approximate Model for Negative PSRR with VBias Connected to VSS
M1 M2
M3 M4
M5
M6
M7
Vout
VDD
VSS
VBias
Cc
CII
Vss
CI
Fig. 6.4-6B
VBias connected to VSS
rds7
vout
Zout Vss
rds7
Path through Cgd7
is negligible
What is Zout?
Zout =
Vt
It
⇒ It = gmIIV1 = gmII
 
  
gmIVt
GI+sCI+sCc
Thus, Zout =
GI+s(CI+Cc)
gmIgMII
∴
Vss
Vout
=
1+
rds7
Zout
1 =
s(Cc+CI) + GI+gmIgmIIrds7
s(Cc+CI) + GI
⇒ Pole at
-GI
Cc+CI
The two-stage op amp will never have good PSRR because of the Miller compensation.
Fig.6.4-7B
Vt
rds6||rds7
CI Vout
Cc
+
-
V1
+
gmIVout -
RI gmIIV1
CII+Cgd7 It
CMOS Analog Circuit Design Page 6.5-1
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
SECTION 6.5 - CASCODE OP AMPS
Why Cascode Op Amps?
• Control of the frequency behavior
• Can get more gain by increasing the output resistance of a stage
• In the past section, PSRR of the two-stage op amp was insufficient for many applications
• A two-stage op amp can become unstable for large load capacitors (if nulling resistor is not used)
• We will see in future sections that the cascode op amp leads to wider ICMR and/or smaller power supply
requirements
Where Should the Cascode Technique be Used?
• First stage -
Good noise performance
Requires level translation to second stage
Degrades the Miller compensation
• Second stage -
Self compensating
Increases the efficiency of the Miller compensation
Increases PSRR
CMOS Analog Circuit Design Page 6.5-2
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Use of Cascoding in the First Stage of the Two-Stage Op Amp
-
+ vin
M1 M2
M3 M4
M5
vo1
VDD
VSS
VBias
+
-
R
VBias
2
vin
2
-
+
MC1 MC2
MC3 MC4
-
+ vin
M1 M2
M3 M4
M5
vo1
VDD
VSS
VBias
+
-
R
2
vin
2
-
+
MC1 MC2
MC3 MC4
MB1 MB2
MB3 MB4
MB5
Fig. 6.5-1
-
+
VBias
Implementation of the
floating voltage VBias.
Rout of the first stage is RI ≈ (gmC2rdsC2rds2)||(gmC4rdsC4rds4)
Voltage gain =
vo1
vin
= gm1RI [The gain is increased by approximately 0.5(gMCrdsC)]
As a single stage op amp, the compensation capacitor becomes the load capacitor.
CMOS Analog Circuit Design Page 6.5-3
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Example 6.5-1 Single-Stage, Cascode Op Amp Performance
Assume that all W/L ratios are 10 μm/1 μm, and that IDS1 = IDS2 = 50 μA of single stage op amp.
Find the voltage gain of this op amp and the value of CI if GB = 10 MHz. Use the model parameters of Table
3.1-2.
Solution
The device transconductances are
gm1 = gm2 = gmI = 331.7 μS
gmC2 = 331.7μS
gmC4 = 223.6 μS.
The output resistance of the NMOS and PMOS devices is 0.5 MΩ and 0.4 MΩ, respectively.
∴ RI = 25 MΩ
Av(0) = 8290 V/V.
For a unity-gain bandwidth of 10 MHz, the value of CI is 5.28 pF.
What happens if a 100pF capacitor is attached to this op amp?
GB goes from 10MHz to 0.53MHz.
CMOS Analog Circuit Design Page 6.5-4
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Two-Stage Op Amp with a Cascoded First-Stage
Cc
-
+ vin
M1 M2
M3 M4
M5
vo1
VDD
VSS
VBias
+
-
R
2
vin
2
-
+
MC1 MC2
MC3 MC4
MB1 MB2
MB3 MB4
MB5
-
+
VBias
MT1
MT2
M6
M7
vout
Fig. 6.5-2
• MT1 and MT2 are required for level shifting from the
first-stage to the second.
• The PSRR+ is improved by the presence of MT1
• Internal loop pole at the gate of M6 may cause the
Miller compensation to fail.
• The voltage gain of this op amp could easily be 100,000V/V
σ
jω
p3 p2 p1 z1
Fig. 6.5-2A
CMOS Analog Circuit Design Page 6.5-5
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Two-Stage Op Amp with a Cascode Second-Stage
-
+
vin
M1 M2
M3 M4
M5
M6
M7
vout
VDD
VSS
VBias
+
-
Cc
CL
VBP
VBN
MC6
MC7
Fig. 6.5-3
Rz
Av = gmIgmIIRIRII where gmI = gm1 = gm2, gmII = gm6,
RI =
1
gds2 + gds4
=
2
(λ2 + λ4)ID5
and RII = (gmC6rdsC6rds6)||(gmC7rdsC7rds7)
Comments:
• The second-stage gain has greatly increased improving the Miller compensation
• The overall gain is approximately (gmrds)3 or very large
• Output pole, p2, is approximately the same if Cc is constant
• The RHP is the same if Cc is constant
CMOS Analog Circuit Design Page 6.5-6
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
A Balanced, Two-Stage Op Amp using a Cascode Output Stage
vout =

 
  
gm1gm8
gm3
vin
2 +
gm2gm6
gm4
vin
2 RII
= 
 
  
gm1
2 +
gm2
2 kvin RII = gm1·k·RII vin
where
RII = (gm7rds7rds6)||(gm12rds12rds11)
and
k =
gm8
gm3
=
gm6
gm4
Note that this op amp is balanced because the drain-to-ground loads for M1 and M2 are identical.
TABLE 6.5-1 Pertinent Design Relationships for Balanced, Cascode Output Stage Op Amp.
Slew rate =
Iout
CL
GB =
gm1gm8
gm3CL
Av =
1
2

 
  
gm1gm8
gm3
+
gm2gm6
gm4
RII
Vin(max) = VDD −

 
  
I5
β3
1/2
− |VTO3|(max) +VT1(min) Vin(min) = VSS + VDS5 +

 
  
I5
β1
1/2
+ VT1(min)
-
+
vin
M1 M2
M3
M4
M5
M6
M11
vout
VDD
VSS
VBias
+
-
CL
R1
M9
M10
R2
M14
M15
M8
M12
M7
M13
Fig. 6.5-4
CMOS Analog Circuit Design Page 6.5-7
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Example 6.5-2 Design of Balanced, Cascoded Output Stage Op Amp
The balanced, cascoded output stage op amp is a useful alternative to the two-stage op amp. Its design
will be illustrated by this example. The pertinent design equations for the op amp were given above. The
specifications of the design are as follows:
VDD = −VSS = 2.5 V
Slew rate = 5 V/μs with a 50 pF load
GB = 10 MHz with a 10 pF load
Av ≥ 5000
Input CMR = −1V to +1.5 V
Output swing = ±1.5 V
Use the parameters of Table 3.1-2 and let all device lengths be 1 μm.
Solution
While numerous approaches can be taken, we shall follow one based on the above specifications. The
steps will be numbered to help illustrate the procedure.
1.) The first step will be to find the maximum source/sink current. This is found from the slew rate.
Isource/Isink = CL × slew rate = 50 pF(5 V/μs) = 250 μA
2.) Next some W/L constraints based on the maximum output source/sink current are developed. Under
dynamic conditions, all of I5 will flow in M4; thus we can write
Max. Iout(source) = (S6/S4)I5 and Max. Iout(sink) = (S8/S3)I5
The maximum output sinking current is equal to the maximum output sourcing current if
S3 = S4, S6 = S8, and S10 = S11
CMOS Analog Circuit Design Page 6.5-8
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Example 6.5-2 - Continued
3.) Choose I5 as 100 μA. Remember that this value can always be changed later on if desirable. This current
gives
S6 = 2.5S4 and S8 = 2.5S3
Note that S8 could equal S3 if S11 = 2.5S10. This would minimize the power dissipation.
4.) Next design for ±1.5 V output capability. We shall assume that the output must source or sink the 250μA
at the peak values of output. First consider the negative output peak. Since there is 1 V difference between
VSS and the minimum output, let VDS11(sat) = VDS12(sat) = 0.5 V (we continue to ignore the bulk effects
which should be considered for a more precise design). Under the maximum negative peak assume that I11 =
I12 = 250 μA. Therefore
0.5 =
2I11
K'NS11
=
2I12
K'NS12
=
500 μA
(110 μA/V2)S11
which gives S11 = S12 = 18.2 and S9 = S10 = 18.2. Using the same approach for the positive peak gives
0.5 =
2I6
K'PS6
=
2I7
K'PS7
=
500 μA
(50 μA/V2)S6
which gives S6 = S7 = S8 = 40 and S3 = S4 = (40/2.5) = 16.
5.) Next the values of R1 and R2 are designed. For the resistor of the self-biased cascode we can write
R1 =
VDS12(sat)
250μA = 2kΩ and R2 =
VSD7(sat)
250μA = 2kΩ
CMOS Analog Circuit Design Page 6.5-9
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Example 6.5-2 - Continued
Using this value of R1 (R2) will cause M11 to slightly be in the active region under quiescent conditions. One
could redesign R1 to avoid this but the minimum output voltage under maximum sinking current would not
be realized. The choice is up to the designer and what is important in the circuit performance.
6.) Now we must consider the possibility of conflict among the specifications.
First consider the input CMR. S3 has already been designed as 16. Using ICMR relationship, we find
that S3 should be at least 4.1. A larger value of S3 will give a higher value of Vin(max) so that we continue to
use S3 = 16 which gives Vin(max) = 1.95V.
Next, check to see if the larger W/L causes a pole below the gainbandwidth. Assuming a Cox of
0.4fF/μm2 gives the first-stage pole of
p3 =
-gm3
Cgs3+Cgs8
=
- 2K’PS3I3
2(0.667)(W3L3+W8L8)Cox
= 33.15x109 rads/sec or 5.275GHz
which is much greater than 10GB.
7.) Next we find gm1 (gm2). There are two ways of calculating gm1.
(a.) The first is from the Av specification. The gain is
Av = (gm1/2gm4)(gm6 + gm11) RII
Note that a current gain of k could be introduced by making S6/S4 (S8/S3 = S11/S3) equal to k.
gm6
gm4
=
gm11
gm3
=
2KP’·S6·I6
2KP’·S4·I4
= k
CMOS Analog Circuit Design Page 6.5-10
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Example 6.5-2 - Continued
Calculating the various transconductances we get gm4 = 282.4 μS, gm6 = gm7 = 707 μS, gm11 = gm12 = 707
μS, rds6 = rd7 = 0.16 MΩ, and rds11 = rds12 = 0.2 MΩ. Assuming that the gain Av must be greater than 5000
and k = 2.5 gives gm1 > 72.43 μS.
(b.) The second method of finding gm1 is from the GB specifications. Multiplying the gain by the dominant
pole (1/CIIRII) gives
GB =
gm1(gm6 + gm11)
2gm4CL
Assuming that CL= 10 pF and using the specified GB gives gm1 = 251 μS.
Since this is greater than 72.43μS, we choose gm1 = gm2 = 251μS. Knowing I5 gives S1 = S2 = 11.45 ≈ 12.
8.) The next step is to check that S1 and S2 are large enough to meet the −1V input CMR specification. Use
the saturation formula we find that VDS5 is 0.5248 V. This gives S5 = 6.6 ≈ 7. The gain becomes Av =
6,925V/V and GB = 10 MHz for a 10 pF load. We shall assume that exceeding the specifications in this area is
not detrimental to the performance of the op amp.
9.) With S5 = 7 then we can design S13 from the relationship
S13 =
I13
I5
S5 =
125μA
100μA7 = 8.75
CMOS Analog Circuit Design Page 6.5-11
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Example 6.5-2 - Continued
10.) Finally we need to design the value of VBias, which can be done with the values of S5 and I5 known.
However, M5 is usually biased from a current source flowing into a MOS diode in parallel with the gatesource
of M5. The value of the current source compared with I5 would define the W/L ratio of the MOS
diode.
Table 6.5-2 summarizes the values of W/L that resulted from this design procedure. The power dissipation for
this design is seen to be 2 mW. The next step would be begin simulation.
Table 6.5-2 Summary of W/L Ratios for Example 6.5-2
S1 = S2 = 12
S3 = S4 = 16
S5 = 7
S6 = S7 = S8 = S14 = S15 = 40
S9 = S10 = S11 = S12 = 18.2
S13 = 8.75
CMOS Analog Circuit Design Page 6.5-12
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Technological Implications of the Cascode Configuration
Fig. 6.5-5
Poly I Poly II
n+ n-channel n+
p substrate/well
A B C D
Thin
oxide
A
B
C
D
If a double poly CMOS process is available, internode parasitics can be minimized.
As an alternative, one should keep the drain/source between the transistors to a minimum area.
Fig. 6.5-5A
Poly I
n+ n-channel n+
p substrate/well
A B C D
Thin
oxide
A
B
C
D
Poly I
Minimum Poly
separation
n+ n-channel
CMOS Analog Circuit Design Page 6.5-13
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Input Common Mode Range for Two Types of Differential Amplifier Loads
vicm
M1 M2
M3 M4
M5
VDD
VSS
VBias
+
-
+
-
VSG3
M1 M2
M3 M4
M5
VDD
VSS
VBias
+
-
+
-
VSD3
VBP
+
-
VSD4
+
-
VSD4
VDD-VSG3+VTN
VSS+VDS5+VGS1
Input
Common
Mode
Range
vicm
VDD-VSD3+VTN
VSS+VDS5+VGS1
Input
Common
Mode
Range
Differential amplifier with
a current mirror load. Fig. 6.5-6
Differential amplifier with
current source loads.
In order to improve the ICMR, it is desirable to use current source (sink) loads without losing half the gain.
The resulting solution is the folded cascode op amp.
CMOS Analog Circuit Design Page 6.5-14
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
The Folded Cascode Op Amp
RB
-
+
vin
M1 M2
M4 M5
M6
M11
vout
VDD
VSS
VBias
+
-
R2 CL
M7
M8 M9
M3 M10
Fig. 6.5-7
I3
I4 I5
I6 I7
I1 I2
R1
M13
M14
M12
RA
A B
Comments:
• The bias currents, I4 and I5, should be designed so that I6 and I7 never become zero (i.e. I4=I5=1.5I3)
• This amplifier is nearly balanced (would be exactly if RA was equal to RB)
• Self compensating
• Poor noise performance, the gain occurs at the output so all intermediate transistors contribute to the noise
along with the input transistors. (Some first stage gain can be achieved if RA and RB are greater than gm1
or gm2.
CMOS Analog Circuit Design Page 6.5-15
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Small-Signal Analysis of the Folded Cascode Op Amp
Model:
gm1vin
2 rds1 rds4
rds6
gm6vgs6
R2+
RA
gm2vin
2 rds2 rds5
rds7
gm7vgs7
RII
RB
i10
i10
+
-
vgs7
+
-
vgs6
Fig. 6.5-8
+
-
vout
i7
1
gm10
Recalling what we learned about the resistance looking into the source of the cascode transistor,
RA =
rds6+R2+(1/gm10)
1 + gm6rds6
≈
1
gm6
and RB =
rds7 + RII
1 + gm7rds7
≈
RII
gm7rds7
where RII ≈gm9rds9rds11
The small-signal voltage transfer function can be found as follows. The current i10 is written as
i10 =
-gm1(rds1||rds4)vin
2[RA + (rds1||rds4)] ≈
-gm1vin
2
and the current i7 can be expressed as
i7 =
gm2(rds2||rds5)vin
2

 
  
RII
gm7rds7
+ (rds2||rds5)
=
gm2vin
2

 
  
1 +
RII(gds2+gds5)
gm7rds7
=
gm2vin
2(1+k) where k =
RII(gds2+gds4)
gm7rds7
The output voltage, vout, is equal to the sum of i7 and i10 flowing through Rout. Thus,
vout
vin
= 
 
  
gm1
2 +
gm2
2(1+k) Rout = 

 
2+k
2+2k gmIRout where Rout ≈ gm9rds9rds11||[gm7rds7(rds2||rds5)]
CMOS Analog Circuit Design Page 6.5-16
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Frequency Response of the Folded Cascode Op Amp
The frequency response of the folded cascode op amp is determined primarily by the output pole which is
given as
pout =
-1
RoutCout
where Cout is all the capacitance connected from the output of the op amp to ground.
All other poles must be greater than GB = gm1/Cout. The approximate expressions for each pole is
1.) Pole at node A: pA ≈
-1
RACA
2.) Pole at node B: pB ≈
-1
RBCB
3.) Pole at drain of M6: p6 ≈
-1
(R2+1/gm10)C6
4.) Pole at source of M8: p8 ≈
-gm8
C8
(Note that for the wide-swing cascode mirror, p8 ≈
-gm8rds8gm10
C8
)
5.) Pole at source of M9: p9 ≈
-gm9
C9
6.) Pole at gate of M10: p10 ≈
-gm10
C10
where the approximate expressions are found by the reciprocal product of the resistance and parasitic
capacitance seen to ground from a given node. One might feel that because RB is approximately rds that this
pole might be too small. However, at frequencies where this pole has influence, Cout, causes RII to be much
smaller making pB also non-dominant.
CMOS Analog Circuit Design Page 6.5-17
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
PSRR of the Folded Cascode Op Amp
Consider the following circuit used to model the PSRR-:
Vout
Vss
Cgd11
M11
M9
VDD
R
Fig. 6.5-9A
Vss Vout
Cgd9
Rout
+
-
Cgd9
VGS11
VGSG9
Vss
Vss
Vss
rds11
Cout
rds9
This model assumes that gate, source and drain of M11 and the gate and source of M9 all vary with VSS.
We shall examine Vout/Vss rather than PSRR-. (Small Vout/Vss will lead to large PSRR-.)
The transfer function of Vout/Vss can be found as
Vout
Vss
≈
sCgd9Rout
sCoutRout+1 for Cgd9 < Cout
The approximate PSRR- is sketched on the next page.
CMOS Analog Circuit Design Page 6.5-18
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Frequency Response of the PSRR- of the Folded Cascode Op Amp
Vout
Vss
GB
Cgd9Rout
|PSRR-|
dB
0dB
Fig. 6.5-10A
log10(ω)
1
Cout
Cgd9
Other sources of Vss injection, i.e. rds9
Dominant
pole frequency
|Avd(ω)|
We see that the PSRR of the cascode op amp is much better than the two-stage op amp.
CMOS Analog Circuit Design Page 6.5-19
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Design Approach for the Folded-Cascode Op Amp
Step Relationship/Requirement Design Equation/Constraint Comments
1 Slew Rate I3 = SR·CL
2 Bias currents in output
cascodes
I4 = I5 = 1.2I3 to 1.5I3 Avoid zero current in
cascodes
3 Maximum output voltage,
vout(max) S5=
8I5
KP’VSD5
2 , S7=
8I7
KP’VSD7
2 Let S4=S14=S5 & S13=S6=S7
VSD5(sat) = VSD7(sat) =
0.5[VDD-Vout(min)]
4 Minimum output voltage,
vout(min) S11=
8I11
KN’VDS11
2 , S9 =
8I9
KN’VDS9
2 Let S10=S11 & S8=S9
VDS9(sat) = VDS11(sat) =
0.5(Vout(min)-|VSS|)
5 Self-bias cascode R1 = VSD14(sat)/I14 and R2 = VDS8(sat)/I6
6 GB =
gm1
CL
S1=S2=
gm1
2
KN’I3
=
GB2CL
2
KN’I3
7 Minimum input CM S3 =
2I3
KN’

 
  
Vin(min)-VSSI3
KN’S1
-VT1 2
8 Maximum input CM S4 = S5 =
2I4
KP’(VDD-Vin(max)+VT1)
S4 and S5 must meet or
exceed the requirements
of step 3
9 Differential Voltage Gain vout
vin
= 
 
  
gm1
2 +
gm2
2(1+k) Rout = 

 
2+k
2+2k gmIRout
10 Power dissipation Pdiss = (VDD-VSS)(I3+I12+I10+I11)
CMOS Analog Circuit Design Page 6.5-20
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Example 6.5-3 Design of a Folded-Cascode Op Amp
Follow the above procedure to design the folded-cascode op amp when the slew rate is 10V/μs, the load
capacitor is 10pF, the maximum and minimum output voltages are ±2V for ±2.5V power supplies, the GB is
10MHz, the minimum input common mode voltage is -1.5V and the maximum input common mode voltage
is 2.5V. The differential voltage gain should be greater than 5,000V/V and the power dissipation should be less
than 5mW. Use channel lengths of 1μm.
Solution
Following the approach outlined above we obtain the following results.
I3 = SR·CL = 10x106·10-11 = 100μA
Select I4 = I5 = 125μA.
Next, we see that the value of 0.5(VDD-Vout(max)) is 0.5V/2 or 0.25V. Thus,
S4 = S5 = S14 =
2·125μA
50μA/V2·(0.25V)2 =
2·125·16
50 = 80
and assuming worst case currents in M6 and M7 gives,
S6 = S7 = S13 =
2·125μA
50μA/V2(0.25V)2 =
2·125·16
50 = 80
The value of 0.5(Vout(min)-|VSS|) is also 0.25V which gives the value of S8, S9, S10 and S11 as
S8 = S9 = S10 = S11 =
2·I8
KN’VDS8
2 =
2·125
110·(0.25)2 = 36.36
The value of R1 and R2 is equal to 0.25V/125μA or 2kΩ. In step 6, the value of GB gives S1 and S2 as
S1 = S2 =
GB2·CL
2
KN’I3
=
(20πx106)2(10-11)2
110x10-6·100x10-6 = 35.9
CMOS Analog Circuit Design Page 6.5-21
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Example 6.5-3 - Continued
The minimum input common mode voltage defines S3 as
S3 =
2I3
KN’

 
  
Vin(min)-VSSI3
KN’S1
- VT1
2
=
200x10-6
110x10-6

 
  
-1.5+2.5-
100
110·35.9 -0.75 2
= 20
We need to check that the values of S4 and S5 are large enough to satisfy the maximum input common mode
voltage. The maximum input common mode voltage of 2.5 requires
S4 = S5 ≥
2I4
KP’[VDD-Vin(max)+VT1] =
2·125μA
50x10-6μA/V2[0.7V]2 = 10.2
which is much less than 80. In fact, with S4 = S5 = 80, the maximum input common mode voltage is 3V.
Finally, S12, is given as
S12 =
125
100 S3 = 25
The power dissipation is found to be
Pdiss = 5V(125μA+125μA+125μA) = 1.875mW
The small-signal voltage gain requires the following values to evaluate:
S4, S5, S13, S14: gm = 2·125·50·80 = 1000μS and gds = 125x10-6·0.05 = 6.25μS
S6, S7: gm = 2·75·50·80 = 774.6μS and gds = 75x10-6·0.05 = 3.75μS
S8, S9, S10, S11: gm = 2·75·110·36.36 = 774.6μS and gds = 75x10-6·0.04 = 3μS
S1, S2: gmI = 2·50·110·35.9 = 628μS and gds = 50x10-6(0.04) = 2μS
CMOS Analog Circuit Design Page 6.5-22
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Example 6.5-3 - Continued
Thus,
RII ≈ gm9rds9rds11 = (774.6μS)

 
1
3μS 
  1 3μS = 86.07MΩ
Rout ≈ 86.07MΩ||(774.6μS)

 1
3.75μS 

 
1
2μS+6.25μS = 19.40MΩ
k =
RII(gds2+gds4)
gm7rds7
=
86.07MΩ(2μS+6.25μS)(3.75μS)
774.6μS = 3.4375
The small-signal, differential-input, voltage gain is
Avd = 

 
2+k
2+2k gmIRout = 

 
2+3.4375
2+6.875 0.628x10-3·19.40x106 = 7,464 V/V
The gain is larger than required by the specifications which should be okay.
CMOS Analog Circuit Design Page 6.5-23
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Comments on Folded Cascode Op Amps
• Good PSRR
• Good ICMR
• Self compensated
• Can cascade an output stage to get extremely high gain with lower output resistance (use Miller
compensation in this case)
• Need first stage gain for good noise performance
• Widely used in telecommunication circuits where large dynamic range is required
CMOS Analog Circuit Design Page 6.6-1
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
SECTION 6.6 - SIMULATION AND MEASUREMENT OF OP AMPS
Simulation and Measurement Considerations
Objectives:
• The objective of simulation is to verify and optimize the design.
• The objective of measurement is to experimentally confirm the specifications.
Similarity Between Simulation and Measurement:
• Same goals
• Same approach or technique
Differences Between Simulation and Measurement:
• Simulation can idealize a circuit
• Measurement must consider all nonidealities
CMOS Analog Circuit Design Page 6.6-2
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Simulating or Measuring the Open-Loop Transfer Function of the Op Amp
Circuit (Darkened op amp identifies the op amp under test):
Fig. 6.6-1
+ -
v VOS IN vOUT
VDD
CL RL VSS
Simulation:
This circuit will give the voltage transfer function curve. This curve should identify:
1.) The linear range of operation
2.) The gain in the linear range
3.) The output limits
4.) The systematic input offset voltage
5.) DC operating conditions, power dissipation
6.) When biased in the linear range, the small-signal frequency response can be obtained
7.) From the open-loop frequency response, the phase margin can be obtained (F = 1)
Measurement:
This circuit probably will not work unless the op amp gain is very low.
CMOS Analog Circuit Design Page 6.6-3
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
A More Robust Method of Measuring the Open-Loop Frequency Response
Circuit:
vIN vOUT
VDD
CL RL VSS
C R
Fig. 6.6-2A
Resulting Closed-Loop Frequency Response:
dB
log10(w)
Av(0)
1
RC RC
Av(0)
Op Amp
Open Loop
Frequency
Response
Fig. 6.6-2B
0dB
Make the RC product as large as possible.
CMOS Analog Circuit Design Page 6.6-4
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Example 6.6-1 – Measurement of the Op Amp Open-Loop Gain
Develop the closed-loop frequency response for op amp circuit shown which is used to measure the open-loop
frequency reasponse. Sketch the closed-loop frequency response of the magnitude of Vout/Vin if the low
frequency gain is 4000 V/V, the GB = 1MHz, R = 10MΩ, and C = 10μF. (Ignore RL and CL)
Solution
The open-loop transfer function of the op amp is,
Av(s) =
GB
s +(GB/Av(0)) =
2πx106
s +500π
The closed-loop transfer function of the op
amp can be expressed as,
vOUT = Av(s)

 
 
 
-1/sC
R+(1/sC) vOUT +vIN
= Av(s)

 
 
 
-1/RC
s+(1/RC) vOUT +vIN
∴
vOUT
vIN
=
-[s +(1/RC)]Av(s)
s +(1/RC)+Av(s)/RC
=
-[s +(1/RC)]
s +(1/RC)
Av(s) +1/RC
=
-(s+0.01)
s +0.01
Av(s) +0.01
Substituting, Av(s) gives,
vOUT
vIN
=
-2πx106s -2πx104
(s+0.01)(s+500π)+2πx104 =
-2πx106s -2πx104
s2+500πs +2πx104 =
-2πx106(s +0.01)
(s+41.07)(s+1529.72)
The magnitude of the closed-loop frequency response is plotted above.
-20
0
20
40
60
80
0.001 0.1 10 1000 105 107
Magnitude, dB
Radian Frequency (radians/sec)
|Av(jω)|
Vout(jω)
Vin(jω)
S01E2S2
CMOS Analog Circuit Design Page 6.6-5
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Simulation and Measurement of Open-Loop Frequency Response with Moderate Gain Op Amps
vIN vOUT
VDD
CL RL VSS
R
R
+
-
vi
Fig. 6.6-3
Make R as large and measure vout and vi to get the open loop gain.
CMOS Analog Circuit Design Page 6.6-6
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Simulation or Measurement of the Input Offset Voltage of an Op Amp
VOS
vOUT=VOS
VDD
VSS
R CL RL
+
-
Fig. 6.6-4
Types of offset voltages:
1.) Systematic offset - due to mismatches in current mirrors, exists even with ideally matched transistors.
2.) Mismatch offset - due to mismatches in transistors (normally not available in simulation except through
Monte Carlo methods).
CMOS Analog Circuit Design Page 6.6-7
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Simulation of the Common-Mode Voltage Gain
VOS
vout
VDD
VSS
R CL RL
+ -
vcm
+
-
Fig. 6.6-5
Make sure that the output voltage of the op amp is in the linear region.
CMOS Analog Circuit Design Page 6.6-8
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Measurement of CMRR and PSRR
Configuration:
Note that vI ≈
vOS
1000 or vOS ≈ 1000vI
How Does this Circuit Work?
Note:
1.) PSRR- can be measured similar to PSRR+ by changing only VSS.
2.) The ±1V perturbation can be replaced by a sinusoid to measure CMRR or PSRR as follows:
PSRR+ =
1000·vdd
vos
, PSRR- =
1000·vss
vos
, and CMRR =
1000·vcm
vos
CMRR: PSRR:
1.) Set
VDD’ = VDD + 1V
VSS’ = VSS + 1V
vOUT’ = vOUT + 1V
2.) Measure vOS called vOS1
3.) Set
VDD’ = VDD - 1V
VSS’ = VSS - 1V
vOUT’ = vOUT - 1V
4.) Measure vOS called vOS2
5.) CMRR=
2000
|vOS2-vOS1|
1.) Set
VDD’ = VDD + 1V
VSS’ = VSS
vOUT’ = 0V
2.) Measure vOS called vOS3
3.) Set
VDD’ = VDD - 1V
VSS’ = VSS
vOUT’ = 0V
4.) Measure vOS called vOS4
5.) PSRR+=
2000
|vOS4-vOS3|
vOS
vOUT
VDD
VSS
CL RL
+
-
+
-
100kΩ
100kΩ
10kΩ
10Ω
vSET
vI
Fig. 6.6-6
CMOS Analog Circuit Design Page 6.6-9
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
How Does the Previous Idea Work?
A circuit is shown which is used to measure the CMRR
and PSRR of an op amp. Prove that the CMRR can be
given as
CMRR =
1000 vicm
vos
Solution
The definition of the common-mode rejection ratio is
CMRR =

 
  
Avd
Acm
=
vout
vid
vout
vicm
However, in the above circuit the value of vout is the same so that we get
CMRR =
vicm
vid
But vid = vi and vos ≈ 1000vi = 1000vid ⇒ vid =
vos
1000
Substituting in the previous expression gives,
CMRR =
vicm
vos
1000
=
1000 vicm
vos
vos
vOUT
VDD
CL RL VSS
+
-
+
-
100kΩ
100kΩ
10kΩ
10Ω
vicm
vi
S99FEP7
vicm
CMOS Analog Circuit Design Page 6.6-10
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Simulation of CMRR of an Op Amp
None of the above methods are really suitable for simulation of CMRR.
Consider the following:
VDD
VSS
Vcm
Vout
V2
V1
V2
V1
Av(V1-V2)
Vcm ±AcVcm
Vout
Vcm
Vcm
+
-
Fig. 6.6-7
Vout = Av(V1-V2) ±Acm
 
  
V1+V2
2 = -AvVout ± AcmVcm
Vout =
±Acm
1+Av
Vcm ≈
±Acm
Av
Vcm
∴ |CMRR| =
Av
Acm
=
Vcm
Vout
CMOS Analog Circuit Design Page 6.6-11
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
CMRR of Ex. 6.3-1 using the Above Method of Simulation
45
50
55
60
65
70
75
80
85
10 100 1000 104 105 106 107 108
|CMRR| dB
Frequency (Hz)
-200
-150
-100
-50
0
50
100
150
200
10 100 1000 104 105 106 107 108
Arg[CMRR] Degrees
Frequency (Hz) Fig. 6.6-8
CMOS Analog Circuit Design Page 6.6-12
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Direct Simulation of PSRR
Circuit:
VDD
VSS
Vdd
Vout
V2
V1
V2
V1
Av(V1-V2)
±AddVdd
Vss
Vss = 0
Fig. 6.6-9
+
-
Vout = Av(V1-V2) ±AddVdd = -AvVout ± AddVdd
Vout =
±Add
1+Av
Vdd ≈
±Add
Av
Vdd
∴ PSRR+ =
Av
Add
=
Vdd
Vout
and PSRR- =
Av
Ass
=
Vss
Vout
Works well as long as CMRR is much greater than 1.
CMOS Analog Circuit Design Page 6.6-13
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Simulation or Measurement of ICMR
vIN
vOUT
VDD
VSS
CL RL
+
-
Fig.6.6-10
ICMR
IDD
vOUT
vIN
1
1
Also, monitor
IDD or ISS.
ISS
Initial jump in sweep is due to the turn-on of M5.
Should also plot the current in the input stage (or the power supply current).
CMOS Analog Circuit Design Page 6.6-14
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Measurement or Simulation of the Open-Loop Output Resistance
Method 1:
+
-
vI
vOUT VDD
VSS
RL
+
-
VO1
VO2
vOUT
vI(mV)
Without RL
With RL
VOS
Fig. 6.6-12
Rout = RL

 
  
V01
V02
− 1 or vary RL until VO2 = 0.5VO1 ⇒ Rout = RL
Method 2:
VSS
VDD
+
-
Ro
Rout
vIN
R 100R
Fig. 6.6-13
Rout =

 
  
1
Ro
+
1
100R +
Av
100Ro
-1
≅
100Ro
Av
CMOS Analog Circuit Design Page 6.6-15
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Measurement or Simulation of Slew Rate and Settling Time
vin
vout
VDD
VSS
CL RL
+
-
IDD Settling Error
Tolerance
1
+SR
1
-SR
Peak Overshoot
Feedthrough
vin
vout
Settling Time
Volts
t
Fig. 6.6-14
If the slew rate influences the small signal response, then make the input step size small enough to avoid slew
rate (i.e. less than 0.5V for MOS).
CMOS Analog Circuit Design Page 6.6-16
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Measurement of Phase Margin from Overshoot
It can be shown (Appendix C) that:
Phase Margin (Degrees) = 57.2958cos-1[ 4ζ4+1 - 2ζ2]
Overshoot (%) = 100 exp

 
  
-πζ
1-ζ2
0
10
20
30
40
50
60
70
80
Phase Margin (Degrees)
1.0
10
0 0.2 0.4 0.6 0.8 1
Overshoot (%)
Phase Margin Overshoot
100
0.1
ζ= 1
2Q
Fig. 6.6-21
For example, a 5% overshoot corresponds to a phase margin of approximately 64°.
CMOS Analog Circuit Design Page 6.6-17
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Example 6.6-2 Simulation of the CMOS Op Amp of Ex. 6.3-1.
The op amp designed in Example 6.3-
1 and shown in Fig. 6.3-3 is to be analyzed
by SPICE to determine if the specifications
are met. The device parameters to be used
are those of Tables 3.1-2 and 3.2-1. In
addition to verifying the specifications of
Example 6.3-1, we will simulate PSRR+ and
PSRR-.
Solution/Simulation
The op amp will be treated as a
subcircuit in order to simplify the repeated
analyses. Table 6.6-1 gives the SPICE
subcircuit description of Fig. 6.3-3. While
the values of AD, AS, PD, and PS could be
calculated if the physical layout was
complete, we will make an educated estimate of these values by using the following approximations.
AS = AD ≅ W[L1 + L2 + L3]
PS = PD ≅ 2W + 2[L1 + L2 + L3]
where L1 is the minimum allowable distance between the polysilicon and a contact in the moat (Rule 5C of
Table 2.6-1), L2 is the length of a minimum-size square contact to moat (Rule 5A of Table 2.6-1), and L3 is
the minimum allowable distance between a contact to moat and the edge of the moat (Rule 5D of Table 2.6-
1).
-
+
vin
M1 M2
M3 M4
M5
M6
M7
vout
VDD = 2.5V
VSS = -2.5V
Cc = 3pF
CL =
10pF
3μm
1μm
3μm
1μm
15μm
1μm
15μm
1μm
M8
4.5μm
1μm
30μA
4.5μm
1μm
14μm
1μm
94μm
1μm
30μA
95μA
Fig. 6.3-3
CMOS Analog Circuit Design Page 6.6-18
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Example 6.6-2 - Continued
Op Amp Subcircuit:
-
+
vin vout
VDD
VSS
+
-
66
2
1
8
9 Fig. 6.6-14A
.SUBCKT OPAMP 1 2 6 8 9
M1 4 2 3 3 NMOS1 W=3U L=1U AD=18P AS=18P PD=18U PS=18U
M2 5 1 3 3 NMOS1 W=3U L=1U AD=18P AS=18P PD=18U PS=18U
M3 4 4 8 8 PMOS1 W=15U L=1U AD=90P AS=90P PD=42U PS=42U
M4 5 4 8 8 PMOS1 W=15U L=1U AD=90P AS=90P PD=42U PS=42U
M5 3 7 9 9 NMOS1 W=4.5U L=1U AD=27P AS=27P PD=21U PS=21U
M6 6 5 8 8 PMOS1 W=94U L=1U AD=564P AS=564P PD=200U PS=200U
M7 6 7 9 9 NMOS1 W=14U L=1U AD=84P AS=84P PD=40U PS=40U
M8 7 7 9 9 NMOS1 W=4.5U L=1U AD=27P AS=27P PD=21U PS=21U
CC 5 6 3.0P
.MODEL NMOS1 NMOS VTO=0.70 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7
+MJ=0.5 MJSW=0.38 CGBO=700P CGSO=220P CGDO=220P CJ=770U CJSW=380P
+LD=0.016U TOX=14N
.MODEL PMOS1 PMOS VTO=-0.7 KP=50U GAMMA=0..57 LAMBDA=0.05 PHI=0.8
+MJ=0.5 MJSW=.35 CGBO=700P CGSO=220P CGDO=220P CJ=560U CJSW=350P +LD=0.014U TOX=14N
IBIAS 8 7 30U
.ENDS
CMOS Analog Circuit Design Page 6.6-19
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Example 6.6-2 - Continued
PSPICE Input File for the Open-Loop Configuration:
EXAMPLE 6.6-2 OPEN LOOP CONFIGURATION
.OPTION LIMPTS=1000
VIN+ 1 0 DC 0 AC 1.0
VDD 4 0 DC 2.5
VSS 0 5 DC 2.5
VIN - 2 0 DC 0
CL 3 0 10P
X1 1 2 3 4 5 OPAMP
...
(Subcircuit of previous slide)
...
.OP
.TF V(3) VIN+
.DC VIN+ -0.005 0.005 100U
.PRINT DC V(3)
.AC DEC 10 1 10MEG
.PRINT AC VDB(3) VP(3)
.PROBE (This entry is unique to PSPICE)
.END
CMOS Analog Circuit Design Page 6.6-20
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Example 6.6-2 - Continued
Open-loop transfer characteristic of Example 6.6-2:
-2
-1
0
1
2
-2 -1.5 -1.0 -0.5 0 0.5 1 1.5 2
vOUT(V)
vIN(mV)
2.5
-2.5
VOS
Fig. 6.6-15B
CMOS Analog Circuit Design Page 6.6-21
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Example 6.6-2 - Continued
Open-loop transfer frequency response of Example 6.3-1:
-40
-20
0
20
40
60
80
10 100 1000 104 105 106 107 108
Magnitude (dB)
Frequency (Hz)
-200
-150
-100
-50
0
50
100
150
200
10 100 1000 104 105 106 107 108
Phase Shift (Degrees)
Frequency (Hz)
GB
100
Phase Margin GB
Fig. 6.6-16B
CMOS Analog Circuit Design Page 6.6-22
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Example 6.6-2 - Continued
Input common mode range of Example 6.3-1:
EXAMPLE 6.6-2 UNITY GAIN CONFIGURATION.
.OPTION LIMPTS=501
VIN+ 1 0 PWL(0 -2 10N -2 20N 2 2U 2 2.01U -2 4U -2 4.01U
+ -.1 6U -.1 6.0 1U .1 8U .1 8.01U -.1 10U -.1)
VDD 4 0 DC 2.5 AC 1.0
VSS 0 5 DC 2.5
CL 3 0 20P
X1 1 3 3 4 5 OPAMP
...
(Subcircuit of Table 6.6-1)
...
.DC VIN+ -2.5 2.5 0.1
.PRINT DC V(3)
.TRAN 0.05U 10U 0 10N
.PRINT TRAN V(3) V(1)
.AC DEC 10 1 10MEG
.PRINT AC VDB(3) VP(3)
.PROBE (This entry is unique to PSPICE)
.END
vin
vout
VDD
VSS
+
-
3
3
1
4
5
Fig. 6.6-16A
Subckt.
-3
-2
-1
0
1
2
3
4
-3 -2 -1 0 1 2 3
vOUT (V)
vIN(V)
ID(M5)
0
10
20
30
40
ID(M5) μA
Input CMR
Fig. 6.6-17B
CMOS Analog Circuit Design Page 6.6-23
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Example 6.6-2 - Continued
Positive PSRR of Example 6.3-1:
-20
0
20
40
60
80
10 100 1000 104 105 106 107 108
|PSRR+(jω)| dB
Frequency (Hz)
-100
-50
0
50
100
10 100 1000 104 105 106 107 108
Arg[PSRR+(jω)] (Degrees)
Frequency (Hz)
100
Fig. 6.6-18B
CMOS Analog Circuit Design Page 6.6-24
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Example 6.6-2 - Continued
Negative PSRR of Example 6.3-1:
10 100 1000 104 105 106 107 108
|PSRR-(jω)| dB
Frequency (Hz)
-200
-150
-100
-50
0
50
100
150
200
10 100 1000 104 105 106 107 108
Arg[PSRR-(jω)] (Degrees)
Frequency (Hz)
20
40
60
80
100
120
Fig. 6.6-19B
PSRR+
CMOS Analog Circuit Design Page 6.6-25
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Example 6.6-2 - Continued
Large-signal and small-signal transient response of Example 6.3-1:
-1.5
-1
-0.5
0
0.5
1
1.5
0 1 2 3 4 5
Volts
Time (Microseconds)
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
2.5 3.0 3.5 4.0 4.5
Volts
Time (Microseconds)
vin(t)
vout(t)
vin(t)
vout(t)
Fig. 6.6-20B
Why the negative overshoot on the slew rate?
If the current sink, M7, cannot sink sufficient current then the output stage
is slewing and it can only respond to changes at the output via the external
feedback path to the input of the amplifier which involves a delay.
Note that -dvout/dt ≈ -2V/0.3μs = -6.67V/μs. For a 10pF capacitor this
requires 66.7μA and only 95μA-66.7μA = 28μA is available for Cc.
For the positive slew rate, M6 can provide whatever current is required by
the capacitors and can immediately respond to changes at the output.
M6
M7
vout
VDD
VSS
VBias
-
Cc
CL
+
95μA
iCc iCL dvout
dt
CMOS Analog Circuit Design Page 6.6-26
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Example 6.6-2 - Continued
Comparison of the Simulation Results with the Specifications of Example 6.3-1:
Specification
(Power supply = ±2.5V)
Design
(Ex. 6.3-1)
Simulation
(Ex. 6.6-2)
Open Loop Gain >5000 10,000
GB (MHz) 5 MHz 5 MHz
Input CMR (Volts) -1V to 2V -1.2 V to 2.4 V,
Slew Rate (V/μsec) >10 (V/μsec) +10, -7(V/μsec)
Pdiss (mW) < 2mW 0.625mW
Vout range (V) ±2V +2.3V, -2.2V
PSRR+ (0) (dB) - 87
PSRR- (0) (dB) - 106
Phase margin (degrees) 60° 65°
Output Resistance (kΩ) - 122.5kΩ
CMOS Analog Circuit Design Page 6.6-27
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Example 6.6-3
Why is the negative-going overshoot larger than the positive-going overshoot on the small-signal transient
response of Example 6.6-2 (right-hand figure of page 6.6-24)?
Solution
Consider the following circuit and waveform:
M6
M7
vout
VDD = 2.5V
VSS = -2.5V
Cc
CL
VBias
95μA
94/1
i6
iCL
0.1V
-0.1V
0.1μs 0.1μs
t
Fig. 6.6-22
iCc
During the rise time, iCL = CL(dvout/dt )= 10pF(0.2V/0.1μs) = 20μA and iCc = 3pf(2V/μs) = 6μA
∴ i6 = 95μA + 20μA + 6μA = 121μA ⇒ gm6 = 1066μS (nominal was 942.5μS)
During the fall time, iCL = CL(-dvout/dt )= 10pF(-0.2V/0.1μs) = -20μA and iCc = -3pf(2V/μs) = -6μA
∴ i6 = 95μA - 20μA - 6μA = 69μA ⇒ gm6 = 805μS
The dominant pole is p1 ≈ (RIgm6RIICc)-1 where RI = 0.694MΩ, RII = 122.5kΩ and Cc = 3pF.
∴ p1(95μA) = 4,160 rads/sec, p1(121μA) = 3,678 rads/sec, and p1(69μA) = 4,870 rads/sec.
CMOS Analog Circuit Design Page 6.6-28
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Thus, the phase margin is less during the fall time than the rise time.
CMOS Analog Circuit Design Page 6.7-1
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
SECTION 6.7 - MACROMODELS FOR OP AMPS
Macromodel
A macromodel is a model that captures some or all of the performance of a circuit using different
components (generally simpler).
A macromodel uses resistors, capacitors, inductors, controlled sources, and some active devices (mostly
diodes) to capture the essence of the performance of a complex circuit like an op amp without modeling every
internal component of the op amp.
Op Amp Characterization
• Small signal, frequency independent
• Small signal, frequency dependent
• Large signal
Time independent
Time dependent
CMOS Analog Circuit Design Page 6.7-2
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Small Signal, Frequency Independent, Op Amp Models
Simple Model
vo
v1
v2
A Rid
v1
v2
Ro
vo
3
1
2
Avd
Ro
(v1-v2)
vo
Rid
v1
v2
Ro
Avd(v1-v2)
3
1
2
4
(a.) (b.) (c.)
Figure 6.7-1 - (a.) Op amp symbol. (b.) Thevenin form of simple model. (c.) Norton form of simple model.
SPICE Description of Fig. 6.7-1c
RID 1 2 {Rid}
RO 3 0 {Ro}
GAVD 0 3 1 2 {Avd/Ro}
Subcircuit SPICE Description for Fig. 6.7-1c
.SUBCKT SIMPLEOPAMP 1 2 3
RID 1 2 {Rid}
RO 3 0 {Ro}
GAVD 0 3 1 2 {Avd/Ro}
.ENDS SIMPLEOPAMP
CMOS Analog Circuit Design Page 6.7-3
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Example 6.7-1 - Use of the Simple Op Amp Model
Use SPICE to find the voltage gain, vout/vin, the input resistance, Rin, and the output resistance, Rout of Fig. 6.7-
2. The op amp parameters are Avd = 100,000, Rid = 1MΩ, and Ro = 100Ω. We want to find the input
resistance, Rin, the output resistance, Rout, and the voltage gain, Av, of the noninverting voltage amplifier
configuration when R1 = 1kΩ and R2 = 100kΩ.
Solution
The circuit with the SPICE node numbers is shown in Fig. 6.7-2.
+
-
vin
vout
R1 = R2 = 100kΩ
1kΩ
1
3
2
A1
Rin Rout
Figure 6.7-2 - Noninverting voltage amplifier for Ex. 6.7-1.
The input file for this example is given as follows.
Example 6.7-1
VIN 1 0 DC 0 AC 1
XOPAMP1 1 3 2 SIMPLEOPAMP
R1 3 0 1KOHM
R2 2 3 100KOHM
.SUBCKT SIMPLEOPAMP 1 2 3
RID 1 2 1MEGOHM
RO 3 0 100OHM
GAVD/RO 0 3 1 2 1000
.ENDS SIMPLEOPAMP
.TF V(2) VIN
.END
The command .TF finds the small signal input resistance, output resistance, and
voltage or current gain of an amplifier. The results extracted from the output file
are:
**** SMALL-SIGNAL CHARACTERISTICS
V(2)/VIN = 1.009E+02
INPUT RESISTANCE AT VIN = 9.901E+08
OUTPUT RESISTANCE AT V(2) = 1.010E-01.
CMOS Analog Circuit Design Page 6.7-4
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Common Mode Model
Electrical Model:
vo = Avd(v1-v2) +
Acm
Ro

 
v1+v2
2
Macromodel:
Rid
1
2
Ric1
Ric2
vo
-
+
3
Ro
Linear Op Amp Macromodel
Avcv1
2Ro
Avcv2
A 2Ro vd(v1-v2)
Ro
Figure 6.7-3 - Simple op amp model including differential and common mode behavior.
SPICE File:
.SUBCKT LINOPAMP 1 2 3
RIC1 1 0 {Ric}
RID 1 2 {Rid}
RIC2 2 0 {Ric}
GAVD/RO 0 3 1 2 {Avd/Ro}
GAVC1/RO 0 3 1 0 {Avc/2Ro}
GAVC2/RO 0 3 2 0 {Avc/2Ro}
RO 3 0 {Ro}
.ENDS LINOPAMP
PARAM OPTION
.SUBCKT LINOPAMP 1 2 3 PARAM:
RICRES=100MEG, RIDRES=1MEG,
+ AVD/RO=10K, AVC/RO=1, RORES=100
RIC1 1 0 RICRES
RID 1 2 RIDRES
RIC2 2 0 RICRES
GAVD/RO 0 3 1 2 AVD/RO
GAVC1/RO 0 3 1 0 AVC/RO
GAVC2/RO 0 3 2 0 AVC/RO
RO 3 0 RORES
.ENDS LINOPAMP
CMOS Analog Circuit Design Page 6.7-5
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Small Signal, Frequency Dependent Op Amp Models
Dominant Pole Model
Avd(s) =
Avd(0)
(s/ω1) + 1) where ω1=
1
R1C1
(dominant pole)
Model Using Passive Components
Rid
v1
v2
vo
1 3
2
R1 C1
Avd(0)
R1
(v1-v2)
Figure 6.7-4 - Macromodel for the op amp including the frequency response of Avd.
Model Using Passive Components with Constant Output Resistance
Rid
v1
v2
vo
1 3
2
R1 C1 Ro
v3
Ro
4
Avd(0)
R1
(v1-v2)
Figure 6.7-5 - Frequency dependent model with constant output resistance.
CMOS Analog Circuit Design Page 6.7-6
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Example 6.7-2 - Frequency Response of the Noninverting Voltage Amplifier
Use the model of Fig. 4 to find the frequency response of Fig. 6.7-2 if the gain is +1, +10, and +100 V/V
assuming that Avd(0) = 105 and ω1= 100 rads/sec.
Solution
The parameters of the model are R2/R1 = 0, 9, and 99. Let us additionally select Rid = 1MΩ and Ro =
100Ω. We will use the circuit of Fig. 2 and insert the model as a subcircuit. The input file for this example is
shown below.
Example 6.7-2
VIN 1 0 DC 0 AC 1
*Unity Gain Configuration
XOPAMP1 1 31 21 LINFREQOPAMP
R11 31 0 15GOHM
R21 21 31 1OHM
*Gain of 10 Configuration
XOPAMP2 1 32 22 LINFREQOPAMP
R12 32 0 1KOHM
R22 22 32 9KOHM
*Gain of 100 Configuration
XOPAMP3 1 33 23 LINFREQOPAMP
R13 33 0 1KOHM
R23 23 33 99KOHM
.SUBCKT LINFREQOPAMP 1 2 3
RID 1 2 1MEGOHM
GAVD/RO 0 3 1 2 1000
R1 3 0 100
C1 3 0 100UF
.ENDS
.AC DEC 10 100 10MEG
.PRINT AC V(21) V(22) V(23)
.PROBE
.END
CMOS Analog Circuit Design Page 6.7-7
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Example 6.7-2 - Continued
-20dB
-10dB
0dB
10dB
20dB
30dB
40dB
100Hz 1kHz 10kHz 100kHz 1MHz 10MHz
Gain of 100
Gain of 10
Gain of 1
15.9kHz 159kHz 1.59MHz
Figure 6.7-6 - Frequency response of the 3 noninverting voltage amplifiers of Ex. 6.7-2.
CMOS Analog Circuit Design Page 6.7-8
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Behavioral Frequency Model
Use of Laplace behavioral modeling capability in PSPICE.
GAVD/RO 0 3 LAPLACE {V(1,2)} = {1000/(0.01s+1)}.
Implements,
GAvd/Ro =
Avd(s)
Ro
=
Avd(0)
Ro
s
ω1
+ 1
where Avd(0) = 100,000, Ro = 100Ω, and ω1 = 100 rps
CMOS Analog Circuit Design Page 6.7-9
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Differential and Common Mode Frequency Dependent Models
Rid
1
2
Ric1
Ric2
vo
-
+
3
Op Amp Macromodel
Avcv1
2Ro
Avcv2
2Ro
Avd(v1-v2)
Ro
v3
Ro
R1
C2 R2
C1
4
5
Ro
v4
Ro
Figure 6.7-7 - Op amp macromodel for separate differential and common voltage gain frequency responses.
CMOS Analog Circuit Design Page 6.7-10
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Zeros in the Transfer Function
Models:
3
Avd(v1-v2)
R1
C1 R1 vo
-
+
v3
Ro
Ro kAvd
Ro
(v1-v2)
4
(a.) (b.)
3
Avd(v1-v2)
Ro
Ro
L1
vo
-
+
4
Figure 6.7-8 - (a.) Independent zero model. (b.) Method of modeling zeros without introducing new nodes.
Inductor:
Vo(s) =

 
  
Avd(0)
Ro
(sL1 + Ro) [V1(s)-V2(s)] = Avd(0)

 
  
s
Ro/L1
+ 1 [V1(s)-V2(s)] .
Feedforward:
Vo(s) =

 
  
Avd(0)
(s/ω1) +1 [ 1+k(s/ω1)+k] [V1(s)-V2(s)] .
The zero can be expressed as
z1 = -ω1

 
1 +
1
k
where k can be + or - by reversing the direction of the current source.
CMOS Analog Circuit Design Page 6.7-11
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Example 6.7-3 - Modeling Zeros in the Op Amp Frequency Response
Use the technique of Fig. 8b to model an op amp with a differential voltage gain of 100,000, a pole at
100rps, an output resistance of 100Ω, and a zero in the right-half, complex frequency plane at 107 rps.
Solution
The transfer function we want to model is given as
Vo(s) =
105(s/107 - 1)
(s/100 + 1) .
Let us arbitrarily select R1 as 100kΩ which will make the GAVD/R1 gain unity. To get the pole at 100rps,
C1 = 1/(100R1) = 0.1μF. Next, we want z1 to be 107 rps. Since ω1 = 100rps, then Eq. (6) gives k as -10-5.
The following input file verifies this model.
Example 6.7-3
VIN 1 0 DC 0 AC 1
XOPAMP1 1 0 2 LINFREQOPAMP
.SUBCKT LINFREQOPAMP 1 2 4
RID 1 2 1MEGOHM
GAVD/R1 0 3 1 2 1
R1 3 0 100KOHM
C1 3 0 0.1UF
GV3/RO 0 4 3 0 0.01
GAVD/RO 4 0 1 2 0.01
RO 4 0 100
.ENDS
.AC DEC 10 1 100MEG
.PRINT AC V(2) VDB(2) VP(2)
.PROBE
.END
CMOS Analog Circuit Design Page 6.7-12
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Example 6.7-3 - Continued
The asymptotic magnitude frequency response of this simulation is shown in Fig. 6.7-9. We note that
although the frequency response is plotted in Hertz, there is a pole at 100rps (15.9Hz) and a zero at 1.59MHz
(10Mrps). Unless we examined the phase shift, it is not possible to determine whether the zero is in the RHP
or LHP of the complex frequency axis.
VDB(2)
0dB
20dB
40dB
60dB
80dB
100dB
1Hz 10Hz 100Hz 1kHz 10kHz 100kHz 1MHz 10MHz
15.9Hz or 100rps
1.59MHz or 10Mrps
Frequency
Figure 6.7-9 - Asymptotic magnitude frequency response of the op amp model of Ex. 6.7-3.
CMOS Analog Circuit Design Page 6.7-13
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Large Signal Macromodels for the Op Amp
Output and Input Voltage Limitations
Nonlinear Op
Amp Macromodel
10 vo
-
+
3
Ro
Avcv4
2Ro 11
D6
+
-
+
-
D5
VOH VOL
Avcv5
2Ro
Rid
1
2 5
Ric1
Ric2
7
D1 D2
+
-
+
-
RLIM 4
6
D3 D4
+ 9
-
+
-
RLIM
8
VIH1
VIH2 VIL2
VIL1
Avd
Ro
(v4-v5)
Figure 6.7-10 - Op amp macromodel that limits the input and output voltages.
Subcircuit Description
.SUBCKT NONLINOPAMP 1 2 3
RIC1 1 0 {Ricm}
RLIM1 1 4 0.1
D1 4 6 IDEALMOD
VIH1 6 0 {VIH1}
D2 7 4 IDEALMOD
VIL1 7 0 {VIL1}
RID 4 5 {Rid}
RIC2 2 0 {Ricm}
RLIM2 2 5 0.1
D3 5 8 IDEALMOD
VIH2 8 0 {VIH1}
D4 9 5 IDEALMOD
VIL2 9 0 {VIL2}
GAVD/RO 0 3 4 5 {Avd/Ro}
GAVC1/RO 0 3 4 0 {Avc/Ro}
GAVC2/RO 0 3 5 0 {Avc/Ro}
RO 3 0 {Ro}
D5 3 10 IDEALMOD
VOH 10 0 {VOH}
D6 11 3 IDEALMOD
VOL 11 0 {VOL}
.MODEL IDEALMOD D N=0.001
.ENDS
CMOS Analog Circuit Design Page 6.7-14
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Example 6.7-4 - Illustration of the Voltage Limits of the Op Amp
Use the macromodel of Fig. 6.7-10 to plot vOUT as a function of vIN for the noninverting, unity gain,
voltage amplifier when vIN is varied from -15V to +15V. The op amp parameters are Avd(0) = 100,000, Rid
= 1MΩ, Ricm = 100MΩ, Avc(0) = 10, Ro = 100Ω, VOH = -VOL = 10V, VIH1 =VIH2 = -VIL1 = -VIL2 = 5V.
Solution
The input file for this example is given below.
Example 6.7-4
VIN 1 0 DC 0
XOPAMP 1 2 2 NONLINOPAMP
.SUBCKT NONLINOPAMP 1 2 3
RIC1 1 0 100MEG
RLIM1 1 4 0.1
D1 4 6 IDEALMOD
VIH1 6 0 5V
D2 7 4 IDEALMOD
VIL1 7 0 -5V
RID 4 5 1MEG
RIC2 2 0 100MEG
RLIM2 2 5 0.1
D3 5 8 IDEALMOD
VIH2 8 0 5V
D4 9 5 IDEALMOD
VIL2 9 0 -5v
GAVD/RO 0 3 4 5 1000
GAVC1/2RO 0 3 4 0 0.05
GAVC2/2RO 0 3 5 0 0.05
RO 3 0 100
D5 3 10 IDEALMOD
VOH 10 0 10V
D6 11 3 IDEALMOD
VOL 11 0 -10V
.MODEL IDEALMOD D N=0.0001
.ENDS
.DC VIN -15 15 0.1
.PRINT V(2)
.PROBE
.END
CMOS Analog Circuit Design Page 6.7-15
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Example 6.7-4 - Illustration of the Voltage Limits of the Op Amp - Continued
-7.5V
-5V
-2.5V
0V
2.5V
5V
7.5V
-10V -5V 0V 5V 10V
V(2)
VIN
Figure 6.7-11 - Simulation results for Ex. 6.7-4.
CMOS Analog Circuit Design Page 6.7-16
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Output Current Limiting
Technique:
D1
D2
D3
D4
ILimit
Io Io
Io
2
ILimit
2 Io
2
Io
2
Io
2
ILimit
2
Macromodel for Output Voltage and Current Limiting:
Rid
v1
v2
Ro
vo
1 3
2
Avd
Ro
(v1-v2)
+ 7
-
+ 8
-
D1
D2
D3
D4
D5 D6
ILimit VOH VOL
4
5
6
CMOS Analog Circuit Design Page 6.7-17
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Example 6.7-5 - Influence of Current Limiting on the Amplifier Voltage Transfer Curve
Use the model above to illustrate the influence of current limiting on the voltage transfer curve of an
inverting gain of one amplifier. Assume the VOH = -VOL = 10V, VIH = -VIL = 10V, the maximum output
current is ±20mA, and R1 = R2 = RL = 500Ω where RL is a resistor connected from the output to ground.
Otherwise, the op amp is ideal.
Solution
For the ideal op amp we will choose Avd = 100,000, Rid = 1MΩ, and Ro = 100Ω and assume one cannot
tell the difference between these parameters and the ideal parameters. The remaining model parameters are
VOH = -VOL = 10V and ILimit = ±20mA.
The input file for this simulation is given below.
Example 6.7-5 - Influence of Current Limiting on the Amplifier Voltage Transfer Curve
VIN 1 0 DC 0
R1 1 2 500
R2 2 3 500
RL 3 0 500
XOPAMP 0 2 3 NONLINOPAMP
.SUBCKT NONLINOPAMP 1 2 3
RID 1 2 1MEGOHM
GAVD 0 4 1 2 1000
RO 4 0 100
D1 3 5 IDEALMOD
D2 6 3 IDEALMOD
D3 4 5 IDEALMOD
D4 6 4 IDEALMOD
ILIMIT 5 6 20MA
D5 3 7 IDEALMOD
VOH 7 0 10V
D6 8 3 IDEALMOD
VOL 8 0 -10V
.MODEL IDEALMOD D N=0.00001
.ENDS
.DC VIN -15 15 0.1
.PRINT DC V(3)
.PROBE
.END
CMOS Analog Circuit Design Page 6.7-18
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Example 6.7-5 - Continued
The resulting plot of the output voltage, v3, as a function of the input voltage, vIN is shown in Fig. 6.7-14.
-10V
-5V
0V
5V
10V
V(3)
-15V -10V -5V 0V 5V 10V 15V
VIN
Figure 6.7-14 - Results of Example 6.7-5.
CMOS Analog Circuit Design Page 6.7-19
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Slew Rate Limiting (Time Dependency)
Slew Rate:
dvo
dt =
±ISR
C1
= Slew Rate
Macromodel:
Rid
v1
v2
vo
3
1
2 R1
A C1 vd(0)
R1
(v1-v2)
D1
D2
D3
D4
6
7
Ro
v4-v5
Ro
4
5
ISR
CMOS Analog Circuit Design Page 6.7-20
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Example 6.7-6 - Simulation of the Slew Rate of A Noninverting Voltage Amplifier
Let the gain of a noninverting voltage amplifier be 1. If the input signal is given as
vin(t) = 10 sin(4x105πt)
use the computer to find the output voltage if the slew rate of the op amp is 10V/μs.
Solution
We can calculate that the op amp should slew when the frequency is 159kHz. Let us assume the op amp
parameters of Avd = 100,000, ω1 = 100rps, Rid = 1MΩ, and Ro = 100Ω. The simulation input file based on
the macromodel of Fig. 6.7-15 is given below.
Example 6.7-6 - Simulation of slew rate limitation
VIN 1 0 SIN(0 10 200K)
XOPAMP 1 2 2 NONLINOPAMP
.SUBCKT NONLINOPAMP 1 2 3
RID 1 2 1MEGOHM
GAVD/R1 0 4 1 2 1
R1 4 0 100KOHM
C1 4 5 0.1UF
D1 0 6 IDEALMOD
D2 7 0 IDEALMOD
D3 5 6 IDEALMOD
D4 7 5 IDEALMOD
ISR 6 7 1A
GVO/R0 0 3 4 5 0.01
RO 3 0 100
.MODEL IDEALMOD D N=0.0001
.ENDS
CMOS Analog Circuit Design Page 6.7-21
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
Example 6.7-6 - Continued
The simulation results are shown in Fig. 6.7-16. The input waveform is shown along with the output
waveform. The influence of the slew rate causes the output waveform not to be equal to the input waveform.
-10V
-5V
0V
5V
10V
0μs 2μs 4μs 6μs 8μs 10μs
Input
Voltage
Output
Voltage
Time
Figure 6.7-16 - Results of Ex. 6.7-6 on modeling the slew rate of an op amp.
CMOS Analog Circuit Design Page 6.7-22
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
SPICE Op Amp Library Models
Macromodels developed from the data sheet for various components.
Key Aspects of Op Amp Macromodels
• Use the simplest op amp macromodel for a given simulation.
• All things being equal, use the macromodel with the min. no. of nodes.
• Use the SUBCKT feature for repeated use of the macromodel.
• Be sure to verify the correctness of the macromodels before using.
• Macromodels are a good means of trading simulation completeness for decreased simulation time.
CMOS Analog Circuit Design Page 6.8-1
Chapter 6 - Amplifiers (5/2/01)  P.E. Allen, 2001
SECTION 6.8 - SUMMARY
• Topics
Design of CMOS op amps
Compensation of op amps
- Miller
- Self-compensating
- Feedforward
Two-stage op amp design
Power supply rejection ratio of the two-stage op amp
Cascode op amps
Simulation and measurement of op amps
Macromodels of op amps
• Purpose of this chapter is to introduce the simple two-stage op amp to illustrate the concepts of op amp
design and to form the starting point for the improvement of performance of the next chapter.
• The design procedures given in this chapter are for the purposes of understanding and applying the design
relationships and should not be followed rigorously as the designer gains experience. |
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