A Wideband Low-Power CT Delta-Sigma Modulator for wireless

kevinwjs

1.  INTRODUCTION………………………………………………………………………...1
1.1. Motivation…………………………………………………………………………….1
1.2.  Thesis Organization…………………………………………………………………...4
2.  OVERVIEW OF OVERSAMPLING
 ADC…………………………………………..5
2.1.  Sampling and Quantization…………………………………………………………...5
2.2. Oversampling…………………………………………………………………………8
2.3. Noise Shaping…………………………………………………………………………9
2.4. Multi-Stage Noise Shaping………………………………………………………….13
3.  SYNTHESIS OF CONTINUOUS-TIME
 MODULATOR……….………………...16
3.1.  Impulse Invariant Transformation…………………………………………………...16
3.2.  Simulation-Based Synthesis of a CT Loop Filter……………………………………18
3.3.  Signal Transfer Function (STF)……………………………………………………..23
4.  DESIGN ISSUES OF CONTINUOUS-TIME
 MODULATOR……………………28
4.1. Non-Idealities of CT Integrators…………………………………………………….28
4.1.1.  Finite Gain Bandwidth of Opamp…………………………………………...29
4.1.2.  Variation of RC Time Constant……………………………………………...32
4.2. Non-Idealities of Quantizer………………………………………………………….34
4.2.1.  Quantizer Delay (Excess Loop Delay)………………………………………35
4.2.2.  Real Characteristics of Comparator………………………………………….38
4.3.  Clock Jitter…………………………………………………………………………..41
4.3.1.  Jitter Noise in NRZ DAC……………………………………………………42
4.3.2.  Jitter Noise in RZ DAC……………………………………………………...46
4.4.  Element Mismatch Effects in a Multi-Bit DAC……………………….…………….48
TABLE OF CONTENTS (Continued)
Page
5.  SYSTEM LEVEL DESIGN……..……………………………………………………...51
5.1.  System Level Parameters……………………………………………………………51
5.2. Architecture of the Loop Filter………………………………………………………54
5.3. Noise Budget………………………………………………………………………...58
5.4.  System Level Simulation…………………………………………………………….60
6.  CIRCUIT AND LAYOUT LEVEL DESIGN…………….……………………………62
6.1.  Loop Filter…………………………………………………………………………...62
6.2.  Front-End Circuits…………………………………………………………………...63
6.2.1.  Noise Analysis……………………………………………………………….64
6.2.2.  Opamp Design……………………………………………………………….69
6.2.3.  Current DAC Design...………………………………………………………73
6.3.  Summation Circuits………………………………………………………………….77
6.4. Quantizer…………………………………………………………………………….80
6.5.  Clock Generator……………………………………………………………………..82
6.6.  Interface Circuit……………………………………………………………………...84
6.7.  Time Constant Tuning……………………………………………………………….86
6.8.  Layout Considerations for High Speed Circuits……………………………………..87
7.  CHIP EVALUATION..…………………………………………………………………...90
7.1.  Test Board Design…………………………………………………………………...90
7.2.  Test Environment……………………………………………………………………92
7.3. Measurement Results………………………………………………………………..92
7.3.1.  Problem of the Interface Circuits…………………………………………….93
7.3.2.  Evaluation of MOD2………………………………………………………...95
7.3.3.  Measurement Results………………………………………………………...97
TABLE OF CONTENTS (Continued)
Page
7.4.  Comparison Between This Work and Earlier Reported Designs…………………..101
8.  CONCLUSIONS………………………………………………………………………...103

fanjx

看看什么东西

fanjx

好东西谢谢谢谢

nesta

作者 Chen Xuefeng
导师 GC Temes

xingxp1983

谢谢。

seawang

thanks！