讨论: 2 个 D-Flip Flop 的 区别 , VHDL

lalabu

我写了2种DFF进行比较, 代码如下，本已为simulate 的结果一样，可是事实并非如此。
付上testbench , 有兴趣的朋友可以试一试。
大家讨论一下2 种代码的区别及仿真的结果吧。

-----------------------------------------------------------------
--Type 0 dff
--file name: dff_enable.vhd
-----------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity dff_enable is
port(
clk : in std_logic;
reset  : in std_logic;
en : in std_logic;
d : in std_logic;
q: out std_logic
);
end dff_enable;
architecture rtl of dff_enable is
signal q_reg: std_logic;
signal q_next: std_logic;
begin
     -- DFF
     process (clk, reset)
     begin
     if(reset = '1') then
        q_reg <= '0';
     elsif (clk = '1' and clk'event ) then
    q_reg <= q_next;
     end if;
     end process;
     --next state
     q_next <=  d when en='1' else
                q_reg;
     --output logic
     q <= q_reg;
end rtl;

-----------------------------------------------------------------
--Type 1 dff
--file name: dff_enable1.vhd
-----------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity dff_enable1 is
port(
clk : in std_logic;
reset  : in std_logic;
en : in std_logic;
d : in std_logic;
q: out std_logic
);
end dff_enable1;
architecture rtl of dff_enable1 is
begin
process (clk, reset)
  begin
  if(reset = '1') then
    q <= '0';
  elsif (clk = '1' and clk'event
         and en = '1') then
    q <= d;
  end if;
end process;
end
rtl;

-----------------------------------------------------------------
--testbench
--file name: dff_enable_TB.vhd
-----------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity dff_enable_TB is  -- entity declaration
end dff_enable_TB;
architecture TB of dff_enable_TB is
    signal T_d:  std_logic;
    signal T_clk: std_logic;
    signal T_reset: std_logic;
    signal T_en: std_logic;
    signal T_q: std_logic;
    signal T_q1: std_logic;
   
    component dff_enable
    port(clk : in std_logic;
         reset  : in std_logic;
         en : in std_logic;
         d : in std_logic;
         q: out std_logic
       );
    end component;
        
    component dff_enable1
    port(clk : in std_logic;
         reset  : in std_logic;
         en : in std_logic;
         d : in std_logic;
         q: out std_logic
       );
    end component;
   
begin
    U_DFF: dff_enable port map (T_clk,T_reset,T_en,T_d, T_q);
    U_DFF1: dff_enable1 port map (T_clk,T_reset,T_en,T_d, T_q1);
        -- concurrent process to offer clock signal
    process
    begin
      T_clk <= '0';
         wait for 5 ns;
      T_clk <= '1';
         wait for 5 ns;
    end process;   
   
    process
     
    begin
        
       T_d <= '1';
       T_reset <= '1';
       T_en <= '1';
       wait for 6 ns;
       assert (T_q='0') report "Error1!" severity error;
       T_reset <= '0';   
       T_d <= '0';
       wait for 5ns;
       assert (T_q='0') report "Error1!" severity error;
      
       T_d <= '1';
       wait for 5ns;
       assert (T_q='1') report "Error1!" severity error;
      
       T_en <= '0';
       T_d <= '0';
       wait for 5ns;
       assert (T_q='1') report "Error1!" severity error;
      
      
      
    end process;
   
   
   
end TB;
-----------------------------------------------------------------
configuration CFG_TB of dff_enable_TB is
for TB
end for;
end CFG_TB;
-----------------------------------------------------------------

[ 本帖最后由 lalabu 于 2008-8-14 23:12 编辑 ]