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发表于 2009-12-11 10:33:10
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RINCON MORA的文章Analog IC Design with Low-Dropout Regulators中关于负载模型的说明如下(中文的是我翻译的，便于大家理解，翻译的不好请见谅)：
The actual“load”is difficult to model because of its unpredictable nature—the designer is often unaware of what will ultimately load the regulator, except in application-specific cases. As it applies to the regulator, however, dc current ILOAD, equivalent load resistance rLOAD,and equivalent load capacitance CLOAD are the most important parameters because they set the biasing condition of the regulator and the small-signal loading impedance of the same, which affects its stability conditions. Load current iLOAD spans the maximum range specified for the regulator (e.g., 1–50 mA) and incurs the worst-case load dumps for the system during transient conditions, which amounts to the maximum possible load step in the shortest time possible (e.g., 1– 25 mA in100 ns).
实际的“负载”很难去建模，由于其不可预知的性质---设计者常常意识不到最终的负载会是什么，一些专门定制的应用的情况除外。尽管如此，适用于LDO的负载中，直流电流源IL，等效负载电阻RL，以及等效负载电容CL是最重要的参数，因为这些决定了LDO的同样的偏置条件和小信号负载阻抗，这些都影响到它的稳定性。恒流源IL跨过LDO最大的电流设定范围(比如，1-50mA)，并且在瞬态条件下将引起负载最坏的响应的情况，这相当于在最短可能的时间中出现的最大可能的负载阶跃(比如，在100ns内从1mA上升到25mA)
Not knowing the exact nature of the load makes it impossible to predict rLOAD accurately, yet its impact on stability and circuit requirements can be profound. If a low-power operational amplifier whose lowest impedance path to ground may be a diode-connected transistor(with small-signal resistance 1/gm) in series with an active load(with relatively larger small-signal resistance rds or ro) loads the regulator,the equivalent-load resistance would be on the order of tens to hundreds of kilo-ohms. High-power amplifiers, on the other hand, deliver substantial currents to low-impedance outputs, normally subjecting the supply transistor to its triode region (i.e., low-resistance switch mode) and in series with the low-impedance output. The slewing amplifier therefore establishes a sub-kilo-ohm path from input supply to ground. In the case of digital circuits, like inverters and other CMOS gates, both pull-down and push-up transistors simultaneously conduct shoot-through current during transitions. Although these transitions are short, the equivalent resistance from the supply to ground is the average series combination of two switch-on resistors,both of which are considerably low in value. In the end, rLOAD may span a wide range of resistances.
由于不知道负载的精确性质，所以不可能精确地预测RL，然而它对电路的稳定性和电路条件的影响却是很大的。如果LDO的负载是一个低功率的运放，它最低的对地阻抗的路径可能是二极管连接的管子(小信号阻抗为1/gm)与一个有源负载(小信号阻抗为相对大的rds或者ro)的串联，那么等效负载电阻将会是几十到几百KΩ的电阻。另一方面，大功率的放大器，一般会使供电晶体管进入到三极管区(例如，低电阻的开关模式)，同时串联低阻抗输出，这将传送实际电流给低负载的阻抗。摆率放大器则因此在输入到地之间建立了一个低于1KΩ的路径。在数字电路中，比如反向器和其它的CMOS传输门，下拉和上推的晶体管在转换期间将同时传导冲击电流。虽然这些转换时间很短，但从电源到地的等效电阻相当于两个导通电阻的串联组合，且两个导通管的阻值都是相当地低。因此，RL有可能跨一个很大的电阻范围。
The designer, for reliability concerns, must therefore consider all extreme conditions: (1) load is purely resistive (iLOAD is zero and rLOAD = VOUT/ILOAD) and (2) load is only a current sink (rLOAD is infinitely large or altogether removed). For example, the worst-case (extreme) rLOAD and iLOAD combinations of a 1–50 mA 2.5 V LDO are (1) 2.5 kΩ (2.5 V/1 mA) and 0 mA, (2) 50 Ω (2.5 V/50 mA) and 0 mA, (3) infinite resistance and 1 mA, and (4) infinite resistance and 50 mA,respectively. Simply assuming the load is purely resistive may be unrealistically optimistic or pessimistic. In the case of internally compensated LDOs, for instance, whose output pole is parasitic to the system, a purely resistive load places the output pole at optimistically higher frequencies. Subjecting this LDO to a higher impedance load pulls the output pole to lower frequencies, compromising the stability of the system. Similarly, assuming the load is purely active, that is,only a current sink, may be unrealistically optimistic in the case of externally compensated LDOs, where the dominant low-frequency pole is at the output and a high-impedance load optimistically places this pole at lower frequencies. A lower impedance load pushes the output pole to higher frequencies, closer to the parasitic poles of the system, where stability may be compromised.
从稳定性方面考虑，设计者必须考虑所有最极端的情况：(1)负载时纯阻性的(IL=0,RL=Vout/IL);(2)负载是纯电流源(RL为无穷大或者完全可以移除)。例如，一个2.5V输出电压，供电电流1-50mA的LDO的最差(极端)情况的RL和IL的组合如下：(1)2.5kΩ(2.5 V/1mA)，IL=0mA；(2)50Ω(2.5V/50mA)，IL=0 mA；(3)RL无穷大，IL=1mA；(4)RL无穷大，IL=50mA。简单假定负载是纯阻性的可能是并不实际的过于乐观估计的或过于不利估计的。比如对于内部补偿的LDO，输出极点是附加的次要极点，纯阻性负载会使系统输出寄生极点处在对系统较为有利的高频，如果使这个LDO接上高阻抗负载将会把输出极点拉至低频，从而给系统稳定性打上折扣。同样，假定负载是纯粹恒流源，对于采用外部补偿的LDO来说，将可能是并不实际的乐观条件，这种情况的低频主极点在输出端，高阻抗的负载将会更有利地把这个极点推到更低频位置，而一个低阻抗负载将会把输出极点推向高频，接近系统的次极点，从而使稳定性打折扣。 |
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