一个synplify的doc文档

wangsheng0415 · 发表于 2008-5-23 16:58:30

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文档中的一些内容标题。Lab 1
Basic Synplify RunLab 2
Analyzing Critical Path and Assigning Timing Constraints and AttributesLab 3

FSM
(Finite State Machine) Compiler
Lab 3 –1

RAM Inference

LAB 3: Demonstrating Synplify support for Altera (Flex)

LAB 2a: Demonstrating Synplify support for Virtex

LAB 2b: Demonstrating scan instantiation for xilinx

Synthesizing Your Design With Synplify

Advanced Tips for Tuning the Synplify Process

Using The HDL Analyst

Directives and Attributes

Input and Output Delays

huangliang122 · 发表于 2008-8-19 09:53:38

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xjsend · 发表于 2009-8-8 07:59:15

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iweey · 发表于 2010-12-1 11:22:44

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chenshi811 · 发表于 2011-3-31 11:06:01

正在找相关资料，谢谢了

canito777 · 发表于 2012-10-19 15:15:50

great tutorial and lab docs

学晋 · 发表于 2014-4-10 00:15:18

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pptmaker · 发表于 2018-8-8 21:47:37

Thanks for sharing

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一个synplify的doc文档

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