|
|
马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。
您需要 登录 才可以下载或查看，没有账号？注册
x
推荐好书：
Verilog:Frequently Asked Questions ——Language, Applications and Extensions
Chapter 1 : Basic Verilog discusses a few important constructs of Verilog and comparisons of what their implications mean in a Verilog based environment.
Chapter 2 : RTL Design discusses the various RTL design and synthesis related FAQs. This chapter will be of real interest to the RTL designers as it discusses the comparison of different coding constructs and styles. The chapter also discusses issues seen during design for area, timing, testability and power.
Chapter 3 : Verification emphasizes using Verilog constructs for Verification. The various issues and considerations for design of BusFunctional Model’s and Bus Monitors are discussed in this chapter. This chapter will be of special interest to readers with verification responsibilities.It also discusses the various mechanisms of random stimulus generation and examples of the different mechanisms.
Chapter 4 : Miscellaneous has all the FAQs that do not explicitly fall in any of the above chapters of RTL and Verification. It discusses the subtle and interesting scenarios of using erilog at a system level.
Chapter 5 : Common Mistakes illustrates most of the commonly made mistakes in the use of Verilog for design or verification. The chapter discusses how the functional issues go undetected, even though it goes through the compile stage without any errors. Any workaround’s to prevent or detect these mistakes have also been illustrated appropriately.
Chapter 6 : Verilog during Simulation Regressions illustrates the different requirements seen during simulation regression, and how different constructs of Verilog can be incorporated within the testbench that will help during regressions. |
|
/2 
eetop公众号
创芯大讲堂
创芯人才网
发表于 2008-5-20 09:45:09
楼主
