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AMD
2008
ASIC Design
Part I
1、用cmos搭Z=!( (A&B)| C | D )
2、 To implement any combinational logic, what is the minimum set of logic gate? Why there are so many types of standard cells in the library?
3、What is Register file, one port embedded RAM, two port embedded RAM?
4、Explain how current STA tools calculate the delay using .lib (including cell delay and wire delay)
5、Write a sequence of 3-bit grey code. Can you derive a general equation to convert binary to grey code?
6、Show the IEEE754 binary representation for the floating-point number (10.5)10 in single precision.
7、A,B,C为8bit integer,Z=A*B,Z=A*B+C,比较这两个设计的delay difference,in unit of gate(如:the difference is 4 Full Adder + 1 MUXs)
8、怎样将一个single-bit信号从快时钟域送到慢时钟域,或慢送到快?Multi-bit信号呢?
9、Suppose we have a pipeline which will process the data in 3 cycles. Sometimes the source may have no data to send out, and sometimes the sink may not be able to receive data. Define the interface signals first, and then design the internal control logic. We must keep the throughput 1 data/cycle, and if there are any possibilities the source shall always be able to send out its data.)
10、设计一个计算连续Leading Zeros个数的电路。输入8-bit,输出4-bit。
00001000
0100
00100010
0010
10001000
0000
可以parameterize你的设计吗?其hardware是什么样子的?
11、Design a round-robin arbiter(轮换仲裁) that can accept 8 requests and give grant signals in one cycle.
12、Setup/Hold time,计算电路最大最小延迟
Part II
关于视频的4道题,基础概念
video/image compression 的原理,过程?
H.264 encoding 框图
Part III
几道C、perl编程 |
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