4本powe manage VLSI的书

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VLSI Circuit Design  Methodology Demystified

The widespread acceptance of sophisticated electronic devices in our daily
life and the growing challenges of a more technically oriented future have
created an unprecedented demand for very large scale integration, or VLSI,
circuits. Meeting this demand requires advances in material science and
processing equipment and the ability to use the computer more effectively
to aid the design process. More importantly, it requires a significant number
of qualified and talented individuals to work this ultra-complicated task.
The goal of this book is to equip interested individuals with the essential
knowledge to enter this exciting field and to help those already involved to
reach higher levels of proficiency.
The challenges in VLSI chip development come from several directions.
Market pressure constantly demands shortening of the product development
cycle. The maximization of profit margin requires control of engineering
cost. Furthermore, the product not only has to be successful technically, but
also financially. These challenges put tremendous strain on the execution of
the VLSI chip development process.
The art of VLSI circuit design is dynamic; it evolves constantly with advances
in process technology and innovations in the electronic design automation
(EDA) industry. This is especially true in the area of system-onchip
(SoC) integration. Due to its complexity and dynamic nature, the topic
of VLSI circuit design methodology is not widely taught in universities, nor
is it well understood by many engineers in this industry. The objective of
this book is to give the reader the opportunity to see the whole picture of
how a complex chip is developed, from concept to silicon.
This book primarily addresses the group of people whose main interest is
chip integration. The focus of chip integration is implementation, not the
circuit design itself. Unlike transistor-level circuit designers who spend
most of their time on the architecture, analysis, optimization, and simulation
of small circuit components, chip integration engineers (or implementation
engineers) mostly work on the task of turning a large chip design from a
logic entity (RTL description or netlist) into a physical entity. The spirit embedded
in this activity is “put everything together and make it work,” not
“create/invent something from scratch.” Consequently, working as an IC
implementation engineer requires a unique set of knowledge and skills.
This book has grown out of lecture notes prepared for graduate-level students.
A technical background in introductory-level circuit design courses
and introductory digital logic courses is required to understand its contents.
Due to the dynamic nature of VLSI design methodology, this book is not organized
by chapters; rather, it is organized in a questions-and-answers format.
Further it is organized in the order of chip development: logic design,
logic verification, logic synthesis, place and route, and physical verification.
By demonstrating the key concepts involved in VLSI chip development
process, it is my hope to help readers build a solid foundation for further advancement
in this field.

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This book provides the detailed information on power distribution
network design in integrated circuit chips. Power distribution
network design is a critical part of the job in circuit design and
physical integration for high-speed chips.
The IR drop and di/dt noise associated with the power distribution
networks are crucial to circuit timing and performance. Due
to the complexity of the millions of gates and interconnects in
modern VLSI chips, power network analysis is accomplished using
CAD tools. These tools take the layout database, usually in
GDSII files, extract the RC parasitic for the power distribution
network, and model the current consumption for switching devices.
A fast circuit simulation is done for the electrical model of the
power distribution network in order to determine the IR drop or
other supply voltage noises, as well as the current density of metal
power lines for checking electromigration failures.
In addition, the decoupling capacitors are inserted into the
power network for stabilizing the supply voltages in local regions
where current surges occur from time to time due to clock and logic
operations. The decoupling capacitors and power distribution
networks are required in some optimal form not only on-chip, but
also on the package and at system levels.
This book will explain the design issues, guidelines, examples,
and CAD tools for the power distribution of the VLSI chip and
package. The user guide of the VoltageStorm™ tool from Cadence
Design Systems, Inc. is referred to throughout [51], together with
the author’s experience using this tool in designs.
The book is organized into seven chapters. Chapter 1 is an introduction
to the power supply network, power network modeling,
decoupling capacitors, and process scaling trends. Chapter 2 illustrates
the design perspectives for the power distribution network,
including power network planning, layout specifications, decoupling
capacitance insertion, modeling and analysis of power networks,
and IR drop analysis and reduction. Chapter 3 explores
electromigration phenomena for the on-chip power distribution
network.
Chapter 4 discusses IR drop analysis methodology. It is taken
primarily from the VoltageStorm™ tool, using both static and dynamic
analysis methods. The static method is performed for some
level worst-case IR drop analysis without the knowledge of input
vectors at the chip’s primary inputs. Chapter 5 describes the commands
and user interfaces of the VoltageStorm™ tool from Cadence
Design Systems, Inc. [51]. Chapter 6 lists the microprocessor
design examples, with a focus on on-chip power distribution.
Readers will gain the insights into industry chip design for power
distribution networks from these examples.
Chapter 7 discusses the flip-chip and package design issues,
since the package is a part of the global power distribution. A case
study has been provided in this chapter for selecting the package
options, based on the performance requirements for the power
supply. Power network measurement techniques from silicon are
also discussed at the end of Chapter 7.
A glossary of key words and basic terms is provided at the end
of the book to help understand the basic concepts in VLSI design
and power distribution.
With the continually decreasing supply voltages and the increasing
transistor switching currents on-chip, power supply noises
on-chip remains the challenging issue for high-performance
chip design. More and more research will be needed in the future
in CAD tools for switching current modeling and accurate power
network analysis. The design methodology for power delivery will
need to consider the performance, layout area, and package technology
optimization for future chips.
The author would like to thank Mr. George J. Telecki at John
viii PREFACE
Wiley & Sons, Inc. for providing the chance to get this book published.
He also thanks his co-workers in Intel Corporation, including
David Ayers, Alex Waizman, and Bendik Kleveland. Finally,
he appreciates the strong support from family members, including
wife Huiling Song and two sons Phillip and Michael

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This book discusses state-of-the-art power management techniques of
modern electronic appliances relying on such Very Large Scale Integration
(VLSI) chips as CPUs and DSPs.
It also covers specific circuit design issues and their implications,
including original derivation of important expressions.
This book is geared toward systems and applications, although it
also gets into the specific technical aspects of discrete and integrated
solutions, like the analysis of circuits within the power chips which
power PCs and other modern electronics.
The first half of this book is a good complement to classic semiconductor
text books because it deals with the same complex issues in a
more conversational way. It avoids completely the use of complex
expressions and minimizing the use of formulas to useful ones, that
allow us to plug values in and get an actual result.
The second half of the book is a broad review of the modern technology
landscape seen through the eyes of the power management engineer,
continually challenged by the rising complexity of modern
electronic appliances.
Scope
In this book, power management is covered in its many facets, including
semiconductor manufacturing processes, packages, circuits, functions,
and systems. The first chapter is a general overview of the semiconductor
industry and gives a glimpse of its many accomplishments in a relatively
short time. Semiconductor processes and packages are discussed
in the second chapter. Great effort has been put here in explaining complex
concepts in conversational and intuitive fashion. Chapter 3 is a
guided “tour de force” in analog design building from the transistor up
to higher level functions and leading to the implementation of a
complete voltage regulator. In chapter 4 we discuss a number of popular
DC-DC voltage regulation architectures, each responding to specific
requirements demanded by the application at hand. Similarly in chapter 5
we move on to discuss AC-DC architectures for power conversion. After
the technical foundation is laid with these first 5 chapters, we move to analyze
some of the most popular electronic appliances. In chapter 6 we cover
ultra portable appliances such as cellular telephones, Personal Digital
Assistants (PDAs) and Digital Still Cameras (DSCs) and discuss the amazing
success of these devices and the trend toward convergence leading to
smart phones that incorporate PDAs, DSCs, Global Positioning Systems
(GPS), Internet appliances and more into one small handheld device. Then
in chapter 7 we cover specifically the desktop PC, a resilient device which
continues to reinvent itself and defeat the many attempts by competing
platforms to make it obsolete. Then we go into portable computing with
the notebook PC aspiring to claim the center stage for the coming age of
“computing anywhere, anytime.” Finally some special power management
topics are covered in chapter 8. In closure the appendix section provides
more in dept information about parts discussed in the chapters.

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part4

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by ARM　and Synopsys
The Low Power Methodology Manual is the outcome of a decade-long collaboration
between ARM and Synopsys commercially and the two of us personally. In 1997
ARM and Synopsys worked together to develop a synthesizable ARM7 core. Dave
was the ARM lead on the project; Mike’s team executed the Synopsys side of the
project. This led to a similar project on the ARM9.
Shortly after these projects, the two of us embarked on a series of technology demonstration
projects. We both felt that we needed to use our products as our customers do
in order to understand how to make these products better. So we developed a test chip
that combined ARM and Synopsys IP and took it through to silicon. We did the RTL
design and verification personally, and borrowed resources to do the implementation.
The experience was incredibly illuminating, and we hope it contributed to improving
the IP and tools from both companies.
We quickly realized that low power was one of the key concerns of our customers,
and SoC designers in general. So we followed our initial project with several low
power technology demonstration projects. The final project was the SALT (Synopsys
ARM Low-power Technology demonstrator) project, for which we received working
silicon late last year. These projects explored clock gating, multi-voltage, dynamic
voltage scaling, and power gating. In all these projects we found that there is no substitute
for direct first-hand experience doing low-power IP-based designs. We learned,
in the most concrete way possible, exactly what our customers go through on an SoC
design.
For years we have been talking about writing a book on low power design. With our
experience on the SALT project, our work with customers on low power designs, and our participation in developing the UPF low-power standard, we feel that we are
finally in a position to publish our insights and perspectives.
In doing so, we have enlisted the aid of our co-authors. The two of us are primarily
front-end engineers, with a background in system architecture and RTL design.
Kaijian and Rob bring a great depth of technical expertise in the physical and circuit
design aspects of low power. Alan has developed low power flows for the ARM processors
and did the implementation of SALT. As a result, he brings a unique perspective
on the implementation issues in low power design.

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ya 好东西啊啊