Finite State Machine Datapath Design, Optimization

yimingxn

ABSTRACT
Finite State Machine Datapath Design, Optimization, and Implementation explores the design space
of combined FSM/Datapath implementations. The lecture starts by examining performance issues
in digital systems such as clock skew and its effect on setup and hold time constraints, and the use
of pipelining for increasing system clock frequency. This is followed by definitions for latency and
throughput, with associated resource tradeoffs explored in detail through the use of dataflow graphs
and scheduling tables applied to examples taken from digital signal processing applications. Also,
design issues relating to functionality, interfacing, and performance for different types of memories
commonly found in ASICs and FPGAs such as FIFOs, single-ports, and dual-ports are examined.
Selected design examples are presented in implementation-neutral Verilog code and block diagrams,
with associated design files available as downloads for both Altera Quartus and Xilinx Virtex FPGA
platforms. A working knowledge of Verilog, logic synthesis, and basic digital design techniques is
required. This lecture is suitable as a companion to the synthesis lecture titled Introduction to Logic
Synthesis using Verilog HDL.

risccpu

good,thanks

jackywang629

很好很好!

finalhaven

this is good class to teach
it is good to see

haveok77

thx for sharing dude

alvinact

dddddddddddddddddddddd

ytxing008

好东西，谢谢

lpxiao

没办法，只能刷屏了

lpxiao

让我再来一次，为了这个文件，顶楼主

lpxiao

谢谢楼主了，这是好东西啊